{"id":7634,"date":"2022-09-01T10:59:44","date_gmt":"2022-09-01T08:59:44","guid":{"rendered":"http:\/\/www.sofics.com\/?page_id=3477"},"modified":"2023-11-07T17:51:20","modified_gmt":"2023-11-07T16:51:20","slug":"samsung-foundry","status":"publish","type":"page","link":"https:\/\/sofics.com\/process-types\/foundries\/samsung-foundry\/","title":{"rendered":"Samsung Foundry"},"content":{"rendered":"\n

Why IC designers need custom ESD cells<\/h4>\n\n\n\n
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Chip designers working on ICs produced at Samsung Foundry use General Purpose I\/O (GPIO) library for the chip interfaces. The foundry also provides ESD protection devices in the PDK. For selected processes and interface types the ESD devices distributed by the foundry are developed by Sofics.<\/p>\n<\/div>\n\n\n\n

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\"\"<\/figure>\n<\/div>\n<\/div>\n\n\n\n
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Sofics IP for Samsung Foundry<\/h2>\n\n\n\n
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Process technology covered<\/h4>\n<\/div>\n<\/div>\n\n\n\n
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FinFET technology (14nm, 8nm, 5nm, 4nm)<\/strong><\/a><\/p>\n<\/div>\n<\/div>\n\n\n\n

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Key focus areas<\/h4>\n\n\n\n
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High-speed interfaces<\/h5>\n<\/div>\n\n\n\n
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Die-2-die interface protection<\/h5>\n<\/div>\n<\/div>\n\n\n\n
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Sofics IP is used for many\u00a0high-speed data interfaces<\/strong> (wireless, wired and optical). These interfaces need ESD clamps with low parasitic capacitance<\/strong>. Sofics clamps provide standard ESD robustness and do not require a resistance in the signal path.<\/p>\n<\/div>\n\n\n\n

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To shorten the distance and delay between different functions some customers are using 3D stacking<\/strong> of different dies in a single assembly. The connections between the different dies (die-2-die interfaces<\/strong>) require custom ESD solutions.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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ESD with low capacitance<\/a><\/div>\n<\/div>\n<\/div>\n\n\n\n
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Die-2-die interfaces<\/a><\/div>\n<\/div>\n<\/div>\n<\/div>\n\n\n\n
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Battery powered applications<\/h5>\n<\/div>\n\n\n\n
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Enhanced ESD robustness<\/h5>\n<\/div>\n<\/div>\n\n\n\n
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For certain applications like IoT, edge AI, medical devices, the power consumption must be reduced. The leakage of Sofics\u2019 ESD cells is 100x lower compared to conventional<\/strong>\u00a0approach. Huge improvements can be made in stand-by, sleep, operational modes and during power-cycles.<\/p>\n<\/div>\n\n\n\n

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Some applications require higher ESD robustness, well beyond the typical 2kV HBM. Our ESD clamps can be easily scaled to any ESD\/EOS protection level. We have delivered ESD clamps for 4kV, 8kV HBM as well as for 8kV IEC 61000-4-2.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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Low leakage ESD<\/a><\/div>\n<\/div>\n<\/div>\n\n\n\n
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Clamps with high ESD robustness<\/a><\/div>\n<\/div>\n<\/div>\n<\/div>\n\n\n\n
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High signal voltage tolerance<\/h5>\n<\/div>\n\n\n\n
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<\/h5>\n<\/div>\n<\/div>\n\n\n\n
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Applications designed on advanced FinFET processes typically use low signal voltages below 2V. However, there are several reasons that designers want to use a higher signal voltage like 3.3V<\/strong>. Sofics has developed ESD devices and I\/O circuits that can handle those requirements.<\/p>\n<\/div>\n\n\n\n

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<\/p>\n<\/div>\n<\/div>\n\n\n\n

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High voltage tolerance<\/a><\/div>\n<\/div>\n<\/div>\n\n\n\n
<\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"

Why IC designers need custom ESD cells Chip designers working on ICs produced at Samsung Foundry use General Purpose I\/O (GPIO) library for the chip interfaces. The foundry also provides ESD protection devices in the PDK. For selected processes and interface types the ESD devices distributed by the foundry are developed by Sofics. Sofics IP […]<\/p>\n","protected":false},"author":61765530,"featured_media":419,"parent":7632,"menu_order":2,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_crdt_document":"","footnotes":""},"class_list":["post-7634","page","type-page","status-publish","has-post-thumbnail","hentry"],"yoast_head":"\nSamsung Foundry - Sofics<\/title>\n<meta name=\"description\" content=\"Sofics has proven on-chip ESD protection clamps for several Samsung Foundry processes. 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