{"id":24234080,"date":"2023-11-06T08:05:23","date_gmt":"2023-11-06T16:05:23","guid":{"rendered":"https:\/\/semiengineering.com\/?p=24234080"},"modified":"2023-11-07T09:01:58","modified_gmt":"2023-11-07T17:01:58","slug":"coding-and-debugging-risc-v","status":"publish","type":"post","link":"https:\/\/semiengineering.com\/coding-and-debugging-risc-v\/","title":{"rendered":"Coding And Debugging RISC-V"},"content":{"rendered":"<p>As monolithic device scaling continues to wind down and evolve toward increasingly heterogeneous designs, it has created an inflection point for chip architects to create customized cores that are much more energy efficient and faster than off-the-shelf processors. Zden\u011bk P\u0159ikryl, CTO of Codasip, talks about where RISC-V fits into this picture, using a modular ISA and custom instruction layer to enable differentiation. He also examines the various steps to develop code for RISC-V designs using a front-end high-level programming language, followed by optimization, to produce an assembly or object file, and looks at what LLVM brings to the table.<\/p>\n<p><iframe loading=\"lazy\" src=\"https:\/\/www.youtube.com\/embed\/Mycy30j0YKs\" width=\"480\" height=\"270\" frameborder=\"0\" allowfullscreen=\"allowfullscreen\"><\/iframe><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Customizing designs to improve performance and reduce power.<\/p>\n","protected":false},"author":3,"featured_media":24204653,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_publicize_message":"","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":true,"jetpack_social_options":{"image_generator_settings":{"template":"highway","default_image_id":0,"font":"","enabled":false},"version":2}},"categories":[143,1129],"tags":[6684,4696,174,21124,15650,8304],"class_list":["post-24234080","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-system-level-design-2","category-youtube","tag-codasip","tag-compilers","tag-debug","tag-instruction-set-architecture","tag-open-source-hardware","tag-risc-v"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v27.4 (Yoast SEO v27.4) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Coding And Debugging RISC-V<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/semiengineering.com\/coding-and-debugging-risc-v\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Coding And Debugging RISC-V\" \/>\n<meta property=\"og:description\" content=\"Customizing designs to improve performance and reduce power.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/semiengineering.com\/coding-and-debugging-risc-v\/\" \/>\n<meta property=\"og:site_name\" content=\"Semiconductor Engineering\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/SemiEngineering\" \/>\n<meta property=\"article:published_time\" content=\"2023-11-06T16:05:23+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2023-11-07T17:01:58+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/semiengineering.com\/wp-content\/uploads\/AdobeStock_373262549-scaled.jpeg\" \/>\n\t<meta property=\"og:image:width\" content=\"2560\" \/>\n\t<meta property=\"og:image:height\" content=\"1713\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"Ann Mutschler\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:creator\" content=\"@SemiEngineering\" \/>\n<meta name=\"twitter:site\" content=\"@SemiEngineering\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"Ann Mutschler\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"1 minute\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/semiengineering.com\\\/coding-and-debugging-risc-v\\\/#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/semiengineering.com\\\/coding-and-debugging-risc-v\\\/\"},\"author\":{\"name\":\"Ann Mutschler\",\"@id\":\"https:\\\/\\\/semiengineering.com\\\/#\\\/schema\\\/person\\\/8c85f0b81a231d0bc3fef047e2db05ea\"},\"headline\":\"Coding And Debugging RISC-V\",\"datePublished\":\"2023-11-06T16:05:23+00:00\",\"dateModified\":\"2023-11-07T17:01:58+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/semiengineering.com\\\/coding-and-debugging-risc-v\\\/\"},\"wordCount\":105,\"commentCount\":0,\"image\":{\"@id\":\"https:\\\/\\\/semiengineering.com\\\/coding-and-debugging-risc-v\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/i0.wp.com\\\/semiengineering.com\\\/wp-content\\\/uploads\\\/AdobeStock_373262549-scaled.jpeg?fit=2560%2C1713&ssl=1\",\"keywords\":[\"Codasip\",\"compilers\",\"debug\",\"instruction set architecture\",\"open-source hardware\",\"RISC-V\"],\"articleSection\":[\"System-Level Design\",\"Videos\"],\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"CommentAction\",\"name\":\"Comment\",\"target\":[\"https:\\\/\\\/semiengineering.com\\\/coding-and-debugging-risc-v\\\/#respond\"]}],\"copyrightYear\":\"2023\",\"copyrightHolder\":{\"@id\":\"https:\\\/\\\/semiengineering.com\\\/#organization\"}},{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/semiengineering.com\\\/coding-and-debugging-risc-v\\\/\",\"url\":\"https:\\\/\\\/semiengineering.com\\\/coding-and-debugging-risc-v\\\/\",\"name\":\"Coding And Debugging RISC-V\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/semiengineering.com\\\/#website\"},\"primaryImageOfPage\":{\"@id\":\"https:\\\/\\\/semiengineering.com\\\/coding-and-debugging-risc-v\\\/#primaryimage\"},\"image\":{\"@id\":\"https:\\\/\\\/semiengineering.com\\\/coding-and-debugging-risc-v\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/i0.wp.com\\\/semiengineering.com\\\/wp-content\\\/uploads\\\/AdobeStock_373262549-scaled.jpeg?fit=2560%2C1713&ssl=1\",\"datePublished\":\"2023-11-06T16:05:23+00:00\",\"dateModified\":\"2023-11-07T17:01:58+00:00\",\"author\":{\"@id\":\"https:\\\/\\\/semiengineering.com\\\/#\\\/schema\\\/person\\\/8c85f0b81a231d0bc3fef047e2db05ea\"},\"breadcrumb\":{\"@id\":\"https:\\\/\\\/semiengineering.com\\\/coding-and-debugging-risc-v\\\/#breadcrumb\"},\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\\\/\\\/semiengineering.com\\\/coding-and-debugging-risc-v\\\/\"]}]},{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\\\/\\\/semiengineering.com\\\/coding-and-debugging-risc-v\\\/#primaryimage\",\"url\":\"https:\\\/\\\/i0.wp.com\\\/semiengineering.com\\\/wp-content\\\/uploads\\\/AdobeStock_373262549-scaled.jpeg?fit=2560%2C1713&ssl=1\",\"contentUrl\":\"https:\\\/\\\/i0.wp.com\\\/semiengineering.com\\\/wp-content\\\/uploads\\\/AdobeStock_373262549-scaled.jpeg?fit=2560%2C1713&ssl=1\",\"width\":2560,\"height\":1713,\"caption\":\"Circuit board background of computer motherboard. Mixed media\"},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\\\/\\\/semiengineering.com\\\/coding-and-debugging-risc-v\\\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\\\/\\\/semiengineering.com\\\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Coding And Debugging RISC-V\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\\\/\\\/semiengineering.com\\\/#website\",\"url\":\"https:\\\/\\\/semiengineering.com\\\/\",\"name\":\"Semiconductor Engineering\",\"description\":\"Deep Insights For Chip Engineers\",\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\\\/\\\/semiengineering.com\\\/?s={search_term_string}\"},\"query-input\":{\"@type\":\"PropertyValueSpecification\",\"valueRequired\":true,\"valueName\":\"search_term_string\"}}],\"inLanguage\":\"en-US\"},{\"@type\":\"Person\",\"@id\":\"https:\\\/\\\/semiengineering.com\\\/#\\\/schema\\\/person\\\/8c85f0b81a231d0bc3fef047e2db05ea\",\"name\":\"Ann Mutschler\",\"image\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\\\/\\\/i0.wp.com\\\/semiengineering.com\\\/wp-content\\\/uploads\\\/3.thumbnail.jpg?resize=59%2C80&ssl=1\",\"url\":\"https:\\\/\\\/i0.wp.com\\\/semiengineering.com\\\/wp-content\\\/uploads\\\/3.thumbnail.jpg?resize=59%2C80&ssl=1\",\"contentUrl\":\"https:\\\/\\\/i0.wp.com\\\/semiengineering.com\\\/wp-content\\\/uploads\\\/3.thumbnail.jpg?resize=59%2C80&ssl=1\",\"caption\":\"Ann Mutschler\"},\"description\":\"Ann Mutschler is senior executive editor at Semiconductor Engineering.\",\"url\":\"https:\\\/\\\/semiengineering.com\\\/author\\\/ann\\\/\"}]}<\/script>\n<!-- \/ Yoast SEO Premium plugin. -->","yoast_head_json":{"title":"Coding And Debugging RISC-V","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/semiengineering.com\/coding-and-debugging-risc-v\/","og_locale":"en_US","og_type":"article","og_title":"Coding And Debugging RISC-V","og_description":"Customizing designs to improve performance and reduce power.","og_url":"https:\/\/semiengineering.com\/coding-and-debugging-risc-v\/","og_site_name":"Semiconductor Engineering","article_publisher":"https:\/\/www.facebook.com\/SemiEngineering","article_published_time":"2023-11-06T16:05:23+00:00","article_modified_time":"2023-11-07T17:01:58+00:00","og_image":[{"width":2560,"height":1713,"url":"https:\/\/semiengineering.com\/wp-content\/uploads\/AdobeStock_373262549-scaled.jpeg","type":"image\/jpeg"}],"author":"Ann Mutschler","twitter_card":"summary_large_image","twitter_creator":"@SemiEngineering","twitter_site":"@SemiEngineering","twitter_misc":{"Written by":"Ann Mutschler","Est. reading time":"1 minute"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/semiengineering.com\/coding-and-debugging-risc-v\/#article","isPartOf":{"@id":"https:\/\/semiengineering.com\/coding-and-debugging-risc-v\/"},"author":{"name":"Ann Mutschler","@id":"https:\/\/semiengineering.com\/#\/schema\/person\/8c85f0b81a231d0bc3fef047e2db05ea"},"headline":"Coding And Debugging RISC-V","datePublished":"2023-11-06T16:05:23+00:00","dateModified":"2023-11-07T17:01:58+00:00","mainEntityOfPage":{"@id":"https:\/\/semiengineering.com\/coding-and-debugging-risc-v\/"},"wordCount":105,"commentCount":0,"image":{"@id":"https:\/\/semiengineering.com\/coding-and-debugging-risc-v\/#primaryimage"},"thumbnailUrl":"https:\/\/i0.wp.com\/semiengineering.com\/wp-content\/uploads\/AdobeStock_373262549-scaled.jpeg?fit=2560%2C1713&ssl=1","keywords":["Codasip","compilers","debug","instruction set architecture","open-source hardware","RISC-V"],"articleSection":["System-Level Design","Videos"],"inLanguage":"en-US","potentialAction":[{"@type":"CommentAction","name":"Comment","target":["https:\/\/semiengineering.com\/coding-and-debugging-risc-v\/#respond"]}],"copyrightYear":"2023","copyrightHolder":{"@id":"https:\/\/semiengineering.com\/#organization"}},{"@type":"WebPage","@id":"https:\/\/semiengineering.com\/coding-and-debugging-risc-v\/","url":"https:\/\/semiengineering.com\/coding-and-debugging-risc-v\/","name":"Coding And Debugging RISC-V","isPartOf":{"@id":"https:\/\/semiengineering.com\/#website"},"primaryImageOfPage":{"@id":"https:\/\/semiengineering.com\/coding-and-debugging-risc-v\/#primaryimage"},"image":{"@id":"https:\/\/semiengineering.com\/coding-and-debugging-risc-v\/#primaryimage"},"thumbnailUrl":"https:\/\/i0.wp.com\/semiengineering.com\/wp-content\/uploads\/AdobeStock_373262549-scaled.jpeg?fit=2560%2C1713&ssl=1","datePublished":"2023-11-06T16:05:23+00:00","dateModified":"2023-11-07T17:01:58+00:00","author":{"@id":"https:\/\/semiengineering.com\/#\/schema\/person\/8c85f0b81a231d0bc3fef047e2db05ea"},"breadcrumb":{"@id":"https:\/\/semiengineering.com\/coding-and-debugging-risc-v\/#breadcrumb"},"inLanguage":"en-US","potentialAction":[{"@type":"ReadAction","target":["https:\/\/semiengineering.com\/coding-and-debugging-risc-v\/"]}]},{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/semiengineering.com\/coding-and-debugging-risc-v\/#primaryimage","url":"https:\/\/i0.wp.com\/semiengineering.com\/wp-content\/uploads\/AdobeStock_373262549-scaled.jpeg?fit=2560%2C1713&ssl=1","contentUrl":"https:\/\/i0.wp.com\/semiengineering.com\/wp-content\/uploads\/AdobeStock_373262549-scaled.jpeg?fit=2560%2C1713&ssl=1","width":2560,"height":1713,"caption":"Circuit board background of computer motherboard. Mixed media"},{"@type":"BreadcrumbList","@id":"https:\/\/semiengineering.com\/coding-and-debugging-risc-v\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/semiengineering.com\/"},{"@type":"ListItem","position":2,"name":"Coding And Debugging RISC-V"}]},{"@type":"WebSite","@id":"https:\/\/semiengineering.com\/#website","url":"https:\/\/semiengineering.com\/","name":"Semiconductor Engineering","description":"Deep Insights For Chip Engineers","potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/semiengineering.com\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"en-US"},{"@type":"Person","@id":"https:\/\/semiengineering.com\/#\/schema\/person\/8c85f0b81a231d0bc3fef047e2db05ea","name":"Ann Mutschler","image":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/i0.wp.com\/semiengineering.com\/wp-content\/uploads\/3.thumbnail.jpg?resize=59%2C80&ssl=1","url":"https:\/\/i0.wp.com\/semiengineering.com\/wp-content\/uploads\/3.thumbnail.jpg?resize=59%2C80&ssl=1","contentUrl":"https:\/\/i0.wp.com\/semiengineering.com\/wp-content\/uploads\/3.thumbnail.jpg?resize=59%2C80&ssl=1","caption":"Ann Mutschler"},"description":"Ann Mutschler is senior executive editor at Semiconductor Engineering.","url":"https:\/\/semiengineering.com\/author\/ann\/"}]}},"jetpack_publicize_connections":[],"jetpack_featured_media_url":"https:\/\/i0.wp.com\/semiengineering.com\/wp-content\/uploads\/AdobeStock_373262549-scaled.jpeg?fit=2560%2C1713&ssl=1","jetpack_sharing_enabled":true,"jetpack_shortlink":"https:\/\/wp.me\/p9HsLC-1DGog","_links":{"self":[{"href":"https:\/\/semiengineering.com\/wp-json\/wp\/v2\/posts\/24234080","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/semiengineering.com\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/semiengineering.com\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/semiengineering.com\/wp-json\/wp\/v2\/users\/3"}],"replies":[{"embeddable":true,"href":"https:\/\/semiengineering.com\/wp-json\/wp\/v2\/comments?post=24234080"}],"version-history":[{"count":4,"href":"https:\/\/semiengineering.com\/wp-json\/wp\/v2\/posts\/24234080\/revisions"}],"predecessor-version":[{"id":24234274,"href":"https:\/\/semiengineering.com\/wp-json\/wp\/v2\/posts\/24234080\/revisions\/24234274"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/semiengineering.com\/wp-json\/wp\/v2\/media\/24204653"}],"wp:attachment":[{"href":"https:\/\/semiengineering.com\/wp-json\/wp\/v2\/media?parent=24234080"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/semiengineering.com\/wp-json\/wp\/v2\/categories?post=24234080"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/semiengineering.com\/wp-json\/wp\/v2\/tags?post=24234080"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}