tag: RISC-V

A New Era For Co-Processing
By Brian Bailey - 09 Apr, 2026 - Comments: 0

Key Takeaways: There is no single processor capable of executing everything efficiently, meaning that multiple processors are required. Maximum efficiency is gained by minimizing the movement of data. Architects must maximize efficiency for today's workloads, while also adding enough flexibility to handle tomorrow's. New processor architectures are rapidly evolving thanks to... » read more

Detecting Architectural Vulnerabilities in Closed-Source RISC-V CPUs (CISPA)
By Technical Paper Link - 17 Feb, 2026 - Comments: 0

The paper "RISCover: Automatic Discovery of User-exploitable Architectural Security Vulnerabilities in Closed-Source RISC-V CPUs" was published by researchers at CISPA Helmholtz Center for Information Security. Abstract "The open and extensible RISC-V instruction set has enabled many new CPU vendors and implementations, but most commercial CPUs are closed-source, significantly hindering vul... » read more

Chip Industry Week In Review
By The SE Staff - 13 Feb, 2026 - Comments: 0

Geopolitics U.S. lawmakers are urging tighter export controls on advanced semiconductor manufacturing equipment (SME) to China, warning existing loopholes threaten national security. "China is working to build domestic SME by exploiting access to U.S. and allied subcomponents required to produce tools," states the letter, which also says better coordination with allies is essential. The U.S.... » read more

Does Your RISC-V Core Meet The Standard?
By Brian Bailey - 29 Jan, 2026 - Comments: 0

Key Takeaways Architectural conformance and implementation verification are necessary but different for RISC-V designs, yet few verification engineers have experience on the conformance side. While RISC-V enables flexibility, there is a potential for ecosystem fragmentation. It is mathematically impossible to test every instruction combination, so engineers are moving beyond just "bl... » read more

Will 2026 Be Dominated By AI?
By Brian Bailey - 15 Jan, 2026 - Comments: 0

Many opportunities and problems became highly interlinked in 2025, fueled by the historic growth in everything AI. But how close are we coming to breaking points, and what are people doing to mitigate them? That is the story that will unfold this year. AI's penetration into an increasing number of workloads is placing almost quadratic demands on compute, memory, interconnect, and the archite... » read more

Two-Stage Hardware Fuzzer (TU Darmstadt)
By Technical Paper Link - 01 Jan, 2026 - Comments: 0

A new technical paper titled "GoldenFuzz: Generative Golden Reference Hardware Fuzzing" was published by researchers at TU Darmstadt. Abstract "Modern hardware systems, driven by demands for high performance and application-specific functionality, have grown increasingly complex, introducing large surfaces for bugs and security-critical vulnerabilities. Fuzzing has emerged as a scalable sol... » read more

Tracking Your Preferences
By Brian Bailey - 23 Dec, 2025 - Comments: 0

I like to use my last blog of the year to focus on you, the reader. You provide valuable feedback to me and the rest of the team at Semiconductor Engineering. What do you want to see us write about? How in-depth should things be? This is always a balance between the amount of information provided and the rate at which readers tire with an article. My focus is the channels I write for – Sys... » read more

HW Security: Inner Product Masking With Fault Detection Via ISE (KU Leuven, NUS, Rambus)
By Technical Paper Link - 09 Dec, 2025 - Comments: 0

A new technical paper titled "Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension" was published by researchers at KU Leuven, National University of Singapore, and Rambus. Abstract  "Inner product masking is a well-studied masking countermeasure against side-channel attacks. IPM-FD further extends the IPM scheme with fault detection capabil... » read more

Roadmap for Open-Source Chiplet-Based RISC-V Systems For HPC and AI (ETH Zurich, Univ. of Bologna)
By Technical Paper Link - 25 Nov, 2025 - Comments: 0

A new technical paper titled "Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond" was published by researchers at ETH Zurich and University of Bologna. Abstract: "We present a roadmap for open-source chiplet-based RISC-V systems targeting high-performance computing and artificial intelligence, aiming to close the performance gap to proprietary designs. Starting with Occamy, the f... » read more

Shaping The Future Of AI Processors: A Tech Threads Conversation With Jim Keller
By Nandan Nayampally - 25 Nov, 2025 - Comments: 0

I had the pleasure of hosting renowned computer architect and Tenstorrent CEO Jim Keller, on the latest episode of Baya Systems’ Tech Threads podcast. If you haven’t already, listen to get his insights on the need for “open” intelligence architectures and what would be needed to drive the semiconductor industry forward. What is an “open” intelligent architecture and ecosystem? As... » read more

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