tag: reliability

Enhancing Silicon Reliability With In-System Test And SLM Data
By Adam Cron - 07 Apr, 2026 - Comments: 0

Innovation in semiconductor development and manufacturing shows no signs of slowing down. Ever-larger chips at ever-smaller geometries create new challenges all the time. At the same time, competitive pressures are shrinking time to market (TTM) and putting enormous pressure on project teams. Furthermore, the wide use of electronics in safety-critical applications demands better reliability, av... » read more

What’s Failing At The Interface
By Gregory Haley - 07 Apr, 2026 - Comments: 0

Key Takeaways The interface is where failures in advanced packaging become visible, but it's increasingly not where they originate. Weak interfaces often don't fail at time zero, but they do degrade due to parametric drift and margin erosion that binary test screens miss entirely. The temporary test interconnect is the largest variable in the measurement chain and must be controlled ... » read more

FeFETs With Laminated Gate Stacks For Radiation Resilience in Vertical NAND (Georgia Tech)
By Technical Paper Link - 10 Mar, 2026 - Comments: 0

A new technical paper, "Enabling Radiation Hardness in Solid-State NAND Storage Utilizing a Laminated Ferroelectric Stack," was published by researchers at Georgia Tech. Abstract "NAND flash forms the core of modern solid-state storage, which is critical for data-intensive AI applications, yet charge-trap NAND suffers rapid threshold-voltage (Vth) degradation under ionizing radiation, causi... » read more

Digital Twins: The Cloud’s The Limit
By Ed Sperling - 10 Mar, 2026 - Comments: 1

Key Takeaways Digital twins are gaining traction as a way of testing different options at every step of the design-through-manufacturing flow. AI can be used to glue together disparate data types in multi-physics simulations. The promise of digital twins is huge, but multiple challenges need to be solved before it can live up to its potential. Digital twin technology is draw... » read more

When Cleaning Chips Isn’t Clean Enough
By Gregory Haley - 19 Feb, 2026 - Comments: 0

Key Takeaways Contamination is becoming much more difficult to identify at the most advanced nodes, forcing fabs to rethink how control is achieved. Issues may show up as electrical or statistical anomalies, not particles, and not at time zero. Reliable classification is needed to identify critical contamination and reduce time and effort spent on nuisance failures. For much... » read more

Every Atom Now Counts In Advanced Chip Manufacturing
By Gregory Haley - 22 Jan, 2026 - Comments: 0

Artificial-intelligence workloads are pushing semiconductor design to a point where traditional scaling strategies are running out of room. Performance improvements that once came from shrinking transistors now depend increasingly on how devices are stacked, interconnected, and isolated. Transistor scaling still matters, but advanced device architectures no longer can accommodate the power dens... » read more

Wafer Probe Struggles To Adapt To Multi-Die Assemblies
By Gregory Haley - 13 Jan, 2026 - Comments: 1

Wafer probe, one of the key processes for ensuring reliability in semiconductor manufacturing, is becoming increasingly unreliable in multi-die assemblies and at leading-edge nodes. For much of the semiconductor industry’s history, wafer probe occupied a stable, largely uncontested role in manufacturing. It was understood as a screening step, an electrical checkpoint to identify failing de... » read more

Data Centers Need High Reliability Semiconductors
By Geoff Tate - 12 Jan, 2026 - Comments: 0

“In the world of designing cars, planes, AI factories … you’ve got to be perfect," said Nvidia CEO Jensen Huang on CNBC last month. "And the reason for this is because there is so much at stake.” Cars and planes need to be extremely reliable because people die if they aren’t. In AI data centers, no one dies when systems fail, but the economic impact is gigantic because Amazon, Goog... » read more

Reliability Extension Architecture For Cost-Effective HBM (RPI, ScaleFlux, IBM TJ Watson)
By Technical Paper Link - 01 Jan, 2026 - Comments: 0

A new technical paper titled "Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference" was published by researchers at Rensselaer Polytechnic Institute, ScaleFlux and IBM T.J. Watson Research Center. Abstract "LLM inference is increasingly memory bound, and HBM cost per GB dominates system cost. Current HBM stacks include short on-die ECC that tightens binning, raise... » read more

When To Move To Multi-Die Assemblies
By Ann Mutschler - 23 Dec, 2025 - Comments: 0

As chip designs become larger and more complex, especially for AI and high-performance computing workloads, it's often not feasible to fit everything onto a single planar die. But determining when to move to a multi-die assembly isn't always straightforward. Multi-die approaches have some well-documented benefits. They allow designers to split functions across different dies, which can impro... » read more

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