tag: ISA

Does Your RISC-V Core Meet The Standard?
By Brian Bailey - 29 Jan, 2026 - Comments: 0

Key Takeaways Architectural conformance and implementation verification are necessary but different for RISC-V designs, yet few verification engineers have experience on the conformance side. While RISC-V enables flexibility, there is a potential for ecosystem fragmentation. It is mathematically impossible to test every instruction combination, so engineers are moving beyond just "bl... » read more

Opportunities And Challenges With Open-Source Hardware In System Development
By Roland Jancke - 13 Nov, 2025 - Comments: 0

For many years now, there has been a trend toward open source in the field of system development. It can be seen in software libraries for the product itself as well as in development tools. A clear motivation for open source lies in the fact that not charging license fees makes a product more attractive on the market. It may also enable further development of the software component, dependi... » read more

Future Architecture Technologies: POE2 And vMTE
By Martin Weidmann - 13 Nov, 2025 - Comments: 0

Future Architecture Technologies are features being developed for currently unreleased versions of the Arm architecture. Arm provides the ecosystem with relevant information and specifications in advance, ensuring software support for when new technologies are realized in hardware. This blog introduces two future technologies: Permission Overlay Extension version 2 (POE2), and Virtual T... » read more

RISC-V’s Increasing Influence
By Brian Bailey - 12 Jun, 2025 - Comments: 2

The industry is increasingly talking about benefits brought by the RISC-V architecture, but is it even the right starting point? While it may not be perfect, it may provide the flexibility necessary to move forward gradually. Computer architectures and software have followed in the footsteps of processors developed 80 years ago. They aimed to solve sequential, scalar arithmetic problems usin... » read more

Arm A-Profile Architecture Developments 2023
By Martin Weidmann - 12 Oct, 2023 - Comments: 0

As computing demands continue to evolve with the rise of artificial intelligence (AI) and advancing security threats, it is imperative that the foundational computing architecture at the heart of the world’s devices continues to evolve. This is why our engineering teams add new features and technologies to the pervasive Arm architecture, with the software teams then ensuring that software lan... » read more

RISC-V Customization Gets A Standing Ovation
By Mike Eftimakis - 24 Aug, 2023 - Comments: 0

Processor vendors have always tried to create a large software ecosystem around their products, because it creates stickiness and it naturally “locks-in” large numbers of customers who have invested in the creation of dedicated software. This effect is growing over time as the quantity of software is ever increasing per product: we could talk about more than 100 million lines of code in a c... » read more

The Uncertainties Of RISC-V Compliance
By Ann Mutschler - 22 Jun, 2023 - Comments: 0

How far can a RISC-V design be pushed and still be compliant? The answer isn't always black-and-white because the RISC-V concept is very different from previous open-source projects. But as interest and activity in RISC-V continues to grow, constructive discussions are taking place to address some of the challenges of designing with an open-standard ISA. “The RISC-V standard is somethin... » read more

Capability Hardware Enhanced RISC Instructions (CHERI) For Verification, With Better Memory Safety (Oxford)
By Technical Paper Link - 30 Nov, 2022 - Comments: 0

A technical paper titled "A Formal CHERI-C Semantics for Verification" was published by researchers at University of Oxford. Abstract: "CHERI-C extends the C programming language by adding hardware capabilities, ensuring a certain degree of memory safety while remaining efficient. Capabilities can also be employed for higher-level security measures, such as software compartmentalization, ... » read more

RISC-V Is Thriving: Here’s What You Need to Know
By Steve Brown - 03 Nov, 2022 - Comments: 0

RISC-V, the open-standard Instruction Set Architecture (ISA) conceived by UC Berkeley developers in 2010, is going from strength to strength. The RISC in RISC-V stands for Reduced Instruction Set Computer, meaning it’s designed to simplify each individual instruction given to the computer. As RISC-V is an open standard, anyone can implement, customize, and expand the ISA to suit their r... » read more

5 Good Things About RISC-V
By Filip Benna - 27 Oct, 2022 - Comments: 0

RISC-V has been around for some time now, and if you are here it’s because you have heard of it. But perhaps you still need to be convinced that it is the future? If you still wonder about its potential and benefits, here are five good things about RISC-V. 1. RISC-V is an open standard Let’s start simple. This is nothing new, but let’s be clear on what open standard means. Open stan... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy