tag: design optimization

Balancing Training, Quantization, And Hardware Integration In NPUs
By Ann Mutschler - 26 Jan, 2026 - Comments: 0

Experts At The Table: AI/ML is driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones. Semiconductor Engineering sat down to discuss this with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Qu... » read more

Addressing Critical Tradeoffs In NPU Design
By Ann Mutschler - 21 Jan, 2026 - Comments: 1

Experts At The Table: AI/ML are driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones. Semiconductor Engineering sat down with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Quadric; Steven W... » read more

How And Why To Optimize NPUs
By Ann Mutschler - 15 Jan, 2026 - Comments: 0

Experts At The Table: AI/ML are driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones.  Semiconductor Engineering sat down with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Quadric; Steven... » read more

Thermal Simulation And Optimization in 3D-IC Design (Intel, UCSB, Cadence)
By Technical Paper Link - 22 Oct, 2025 - Comments: 0

A new technical paper titled "DeepOHeat-v1: Efficient Operator Learning for Fast and Trustworthy Thermal Simulation and Optimization in 3D-IC Design" was published by researchers at Intel Corporation, University of California, Santa Barbara and Cadence. Abstract "Thermal analysis is crucial in 3D-IC design due to increased power density and complex heat dissipation paths. Although operator ... » read more

Allegro X AI for Generative System Design
By Cadence - 26 Mar, 2025 - Comments: 0

PCB design is the act of realizing a schematic into a physical form. Currently, human designers use electronic design automation (EDA) software to combine component placement and routing to realize the electrical connectivity on a manufacturable PCB. Computer-aided design (CAD) tools have been used in the design flow since the 1970s and are now an essential part of the designer’s toolkit. Som... » read more

Design Optimization Techniques To Improve NC-CFET Performance
By Technical Paper Link - 14 Mar, 2025 - Comments: 0

A new technical paper titled "Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET)" was published by researchers at National Yang Ming Chiao Tung University. Abstract "This work assesses and analyzes negative-capacitance CFETs (NC-CFETs) with metal-ferroelectric-insulator-semiconductor (MFIS) and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) configu... » read more

Higher Density, More Data Create New Bottlenecks In AI Chips
By Adam Kovac - 12 Sep, 2024 - Comments: 0

Data movement is becoming a bigger problem at advanced nodes and in advanced packaging due to denser circuitry, more physical effects that can affect the integrity of signals or the devices themselves, and a significant increase in data from AI and machine learning. Just shrinking features in a design is no longer sufficient, given the scaling mismatch between SRAM-based L1 cache and digital... » read more

Wafer-Scale Variability In Photonic Devices & Effects On Circuits
By Technical Paper Link - 25 Nov, 2022 - Comments: 0

A technical paper titled "Capturing the Effects of Spatial Process Variations in Silicon Photonic Circuits" was published by researchers at Photonics Research Group, Ghent University−IMEC. "We present in this paper a method to extract a granular map of the line width and thickness variation on a silicon photonics wafer. We propose a hierarchical model to separate the layout-dependent and l... » read more

The Power Of Big Data: Or How To Make Perfect 30-Minute Brownies In Only 30 Minutes
By Mark Richards - 27 Jun, 2022 - Comments: 0

You're scrolling online, and the picture stops you in your tracks, grabs you, captivates you. Glistening chocolate pieces are, determinedly yet slowly, oozing down a moist brownie with a crisped-to-perfection, powdered topping. It sits there, confident, flaking lazily onto a bone-white china plate. It looks delicious—mouthwatering—and, apparently, you can make it with just a 30-minute inves... » read more

Managing Electrical Communications Better
By Ann Mutschler - 14 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Managing the electrical components of signal paths between IC, package, board and system is no small task, and it’s only growing in complexity. Understanding how to correctly optimize the communications within a system is critical given that the I/O power is becoming a significant portion of the overall chip power as the number of bits and the speed at which t... » read more

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