tag: debug

Replay‑based Validation as a Scalable Methodology for Chiplet‑based Systems (Intel, Synopsys)
By Technical Paper Link - 18 Mar, 2026 - Comments: 0

A new technical paper, "ODIN-Based CPU-GPU Architecture with Replay-Driven Simulation and Emulation," was published by researchers at Intel, Nvidia and Synopsys. Abstract "Integration of CPU and GPU technologies is a key enabler for modern AI and graphics workloads, combining control-oriented processing with massive parallel compute capability. As systems evolve toward chiplet-based archite... » read more

Serial Wire Debug (SWD) Protocol: Efficient Debug Interface For Arm-Based Systems
By Divya Chawla - 12 Mar, 2026 - Comments: 0

Modern embedded systems are becoming increasingly compact, power efficient, and feature rich. As SoCs integrate more functionality, developers need reliable debug access without increasing pin count or board complexity. Serial Wire Debug (SWD) addresses these needs by providing a streamlined alternative to JTAG, enabling high performance debug features using only two pins, making it ideal for t... » read more

Autonomous ASIC Root Cause Analysis
By Mehir Arora - 23 Dec, 2025 - Comments: 0

By Mehir Arora and Zackary Glazewski Over 50% of frontend ASIC hardware engineering time is spent on debugging and root cause analysis, spent churning through millions of lines of code and terabytes of waveform data. Despite this, there are no existing solutions for autonomous root cause analysis that use both code and waveform data. ChipAgents Root Cause Analysis (ChipAgents RCA) is the fir... » read more

Beyond The Core: Tackling System-Wide Debugging For Complex SoCs
By Francisca Tan - 09 Dec, 2025 - Comments: 0

The world of System-on-Chips (SoCs) is evolving – with the advancement of generative AI, the increasing demand for high-performance compute, and the innovative shift towards multi-chiplet architectures, system complexity is advancing at an increased pace. And with complexity comes an even greater challenge: debugging complexity. Silent data corruption, elusive timing-sensitive bugs, and i... » read more

2025 Critical Hardware Weaknesses (Hardware CWE Special Interest Group)
By Technical Paper Link - 29 Aug, 2025 - Comments: 0

A new technical paper titled "2025 Most Important Hardware Weaknesses" was published by researchers at Hardware CWE Special Interest Group. Excerpt "The Most Important Hardware Weaknesses (MIHW) empowers organizations with the knowledge to proactively strengthen hardware security and reduce risks at the source. The 2025 CWE MIHW represents a refreshed and enhanced effort to identify and edu... » read more

LLM-Based Chiplet Design Generation Framework (Univ. of Minnesota)
By Technical Paper Link - 29 Aug, 2025 - Comments: 0

A new technical paper titled "MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging" was published by researchers at the University of Minnesota - Twin Cities. Abstract "As program workloads (e.g., AI) increase in size and algorithmic complexity, the primary challenge lies in their high dimensionality, encompassing computing cores, array sizes, and memory hierarch... » read more

How To Transform Verification Time-To-Results
By Priyank Jain - 28 Aug, 2025 - Comments: 0

The clock is ticking. Your team has just completed another full-chip DRC run on a complex 5nm SoC, and the results are overwhelming: millions of violations across hundreds of blocks. With tape-out deadlines approaching, you need to quickly identify which issues are critical, which are systematic and which blocks require immediate attention. Every day spent in DRC debug is a day delayed to marke... » read more

Optimizing System Production with On-Chip Telemetry and ML-Driven Analytics
By proteanTecs - 12 Aug, 2025 - Comments: 0

Abstract As system companies integrate increasingly advanced chips onto their boards for high-performance markets such as AI, Cloud, Telecommunications, and Automotive, the complexity of system production continues to rise. Ensuring quality, performance, and lifetime reliability while minimizing test costs and production time has become a significant challenge.‍ A new solution addres... » read more

Rethinking Chip Debug
By Priyank Jain - 30 Jun, 2025 - Comments: 0

By Priyank Jain and James Paris The semiconductor industry has spent decades mastering the art of integrated circuit physical verification. But as system-on-chip (SoC) designs push the boundaries of complexity—with more transistors, greater integration and larger silicon areas—the established debug strategies are breaking under the weight of scale. Today’s advanced chips can generate a... » read more

Smarter, Faster, Leaner: Rethinking Verification For The Modern Era
By Harry Foster - 12 Jun, 2025 - Comments: 0

Verification isn’t just another step in the semiconductor design process—it’s increasingly the step that defines whether teams hit their schedules or miss the mark. With skyrocketing design complexity, accelerated development timelines, and persistent engineering shortages, the industry is feeling the pressure. Traditional methods aren’t keeping pace. At Siemens, we’ve been rethink... » read more

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