Memory Wall Gets Higher


Key Takeaways An increasing percentage of the chip area is consumed by the same amount of SRAM for each node shrink. The problem is not limited to leading-edge AI, as it will eventually impact even small MCUs and MPUs. Architectural changes may be required. Stacking SRAM chiplets on logic is possible but expensive. SRAM is a vital piece of all computing systems, but its fail... » read more

OTP Dynamic Power Cut By Factor Of 10


Of the challenges being addressed by Internet of Things (IoT) designers around the globe, none is more pressing than the need to reduce edge-node power. While eyes often turn to the radio as primary consumer of energy, memory, including NVM memory, also contributes a substantial portion of the energy consumed by an edge node. Power reductions in all memories will be essential for meeting this c... » read more

Moore Memory Problems


The six-transistor static memory cell (SRAM) has been the mainstay of on-chip memory for several decades and has stood the test of time. Today, many advanced SoCs have 50% of the chip area covered with these memories and so they are critical to continued scaling. “The SRAM being used in modern systems is similar to the SRAM they were using in the 1970s and 1980s,” says Duncan Bremner, ch... » read more