tag: SRAM

Optimizing In-Memory AI Accelerators Across Multiple Workloads (KAUST, Compumacy)
By Technical Paper Link - 06 Mar, 2026 - Comments: 0

Researchers from KAUST and Compumacy for Artificial Intelligence Solutions have released “Joint Hardware-Workload Co-Optimization for In-Memory Computing Accelerators”. Abstract “Software-hardware co-design is essential for optimizing in-memory computing (IMC) hardware accelerators for neural networks. However, most existing optimization frameworks target a single workload, lea... » read more

Optimal Heterogeneous Memory Configs for AI Tasks Under Specified Performance Metrics (Stanford, UCSC)
By Technical Paper Link - 01 Mar, 2026 - Comments: 0

Researchers from Stanford University and University of California, Santa Cruz have released “Heterogeneous Memory Design Exploration for AI Accelerators with a Gain Cell Memory Compiler”. Abstract “As memory increasingly dominates system cost and energy, heterogeneous on-chip memory systems that combine technologies with complementary characteristics are becoming essential. Gain ... » read more

Electrical Model of the Bitflip in SRAM Under Laser Illumination Simulating Laser Fault Injection
By Technical Paper Link - 22 Feb, 2026 - Comments: 0

A new technical paper, "Electrical modelisation of a bitflip in SRAM cell memory induced by laser fault injection," was published by researchers at Univ Rennes, CNRS, IETR. Abstract "An electrical model of the bitflip in SRAM under laser illumination simulating laser fault injection is proposed. This model is based on a bipolar phototransistor responsible of the amplified induced photocur... » read more

Router-in-a-Package Design Combining HBM4, Chiplets and In-Package Optics (Technion, Berkeley, UCSD)
By Technical Paper Link - 18 Feb, 2026 - Comments: 0

A new technical paper "Scaling Routers with In-Package Optics and High-Bandwidth Memories" was posted by researchers at Technion, UC Berkeley and UC San Diego. Abstract "This paper aims to apply two major scaling transformations from the computing packaging industry to internet routers: the heterogeneous integration of high-bandwidth memories (HBMs) and chiplets, as well as in-package optic... » read more

Impact Of On-Chip SRAM Size And Frequency On Energy Efficiency And Performance of LLM Inference (Uppsala Univ.)
By Technical Paper Link - 03 Jan, 2026 - Comments: 0

A new technical paper titled "Prefill vs. Decode Bottlenecks: SRAM-Frequency Tradeoffs and the Memory-Bandwidth Ceiling" was published by researchers at Uppsala University. Abstract "Energy consumption dictates the cost and environmental impact of deploying Large Language Models. This paper investigates the impact of on-chip SRAM size and operating frequency on the energy efficiency and per... » read more

The Impact Of DRAM Writes On DDR5-Based Systems (Georgia Tech)
By Technical Paper Link - 28 Dec, 2025 - Comments: 0

A new technical paper titled "BARD: Reducing Write Latency of DDR5 Memory by Exploiting Bank-Parallelism" was published by Georgia Tech. Abstract "This paper studies the impact of DRAM writes on DDR5-based system. To efficiently perform DRAM writes, modern systems buffer write requests and try to complete multiple write operations whenever the DRAM mode is switched from read to write. Whe... » read more

Multi-Core Architecture Optimized For Time-Predictable Neural Network Inference (FZI, KIT)
By Technical Paper Link - 21 Nov, 2025 - Comments: 0

A new technical paper titled "MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference" was published by researchers at FZI Research Center for Information Technology and Karlsruhe Institute for Information Technology (KIT). Abstract: "Real-time systems, particularly those used in domains like automated driving, are increasingly adopting neural network... » read more

Comparative Analysis of CFET and NSFET Architectures (TU Munich, IIT)
By Technical Paper Link - 14 Nov, 2025 - Comments: 0

A new technical paper titled "Impact of Aging, Self-Heating, and Parasitics Effects on NSFET and CFET" was published by researchers at TU Munich and Indian Institute of Technology. Abstract "This work presents a comparative analysis of complementary field-effect transistor (CFET) and nanosheet FET (NSFET) architectures, with a focus on self-heating effects (SHEs), negative bias temperature ... » read more

The Competitive Advantage Of SRAM PUF Technology
By Vincent van der Leest - 09 Oct, 2025 - Comments: 1

By Vincent van der Leest and Geert-Jan Schrijen In the article from 2024, "SRAM PUF: The Secure Silicon Fingerprint", we explored the fundamentals of SRAM-based Physical Unclonable Functions (PUFs) and their role as a secure, cost-effective, and scalable solution for cryptographic (root) key generation and storage. SRAM PUF technology leverages the unique physical properties of silicon to c... » read more

In-SRAM Computing Architecture Tailored For Cryptographic Acceleration Within MCUs (UC Riverside)
By Technical Paper Link - 06 Oct, 2025 - Comments: 0

A new technical paper titled "CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing" was published by researchers at University of California, Riverside. Abstract "Secure communication is a critical requirement for Internet of Things (IoT) devices, which are often based on Microcontroller Units (MCUs). Current cryptographic solutions, which rely on software librari... » read more

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