Qihe: A General-Purpose Verilog
Static Analysis Framework
Deep Hardware Analysis in the Early Stage of Hardware Development
Well-Organized Comprehensive Analyses Suite
Qihe offers a comprehensive suite of analyses tailored for diverse hardware analysis tasks.
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Hardware Fundamental Analyses
Common Utilities
- Bit-reference analysis: Model bit-level semantics
- Hierarchy analysis: Resolve Verilog module instantiation
- IR statistics collector: Gather design metrics (e.g., number of modules, signals)
Control Flow
- CFG builder: Construct intra-schedule or inter-schedule control flow graphs
- Branch analysis: Find guarding conditions for statements
- Call graph builder: Analyze function call relationships
Data Flow
- Def-use analysis: Find definition or use locations of variables
- VFG builder: Construct flow-insensitive or flow-sensitive value flow graphs
- Reaching definitions analysis: Find available definitions at each program point
- Constant propagation: Bit-level constant propagation handling Verilog's 4-valued logic
Concurrency & Synchronization
- Thread model: Model concurrent always blocks
- Block-level I/O analysis: Analyze signals input or output by always blocks
- Guard analysis: Examine timing controls (e.g., @(posedge clk)) for statement synchronization
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Hardware Bug Analyses
- Missing-reset Analysis: Find registers without proper reset
- Deadlock Analysis: Detect deadlock in sequential logic
- Loop Analysis: Detect combinational loops
- Race Analysis: Find data races in simulation
- Mis-truncation Analysis: Catch unintended data loss from bit-width mismatches
- Undefined-use Analysis: Find signals loaded before being driven
- Invalid-use Analysis: Find signals loaded before a ready/valid signal arrives
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Hardware Security Analyses
- Taint analysis: Track information flow to detect potential data leakages and injection vulnerabilities
- X-value analysis: Identify hardware Trojans exploiting Verilog's special X values
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Hardware Understanding Analyses
- FSM inference: Extract finite state machines
- Latch inference: Detect unintended latch generation
- Register inference: Determine which variables are mapped to physical registers
- Clock inference: Predict the physical clock tree structure
- Reset logic inference: Identify reset logic in designs
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Hardware Optimization Analyses
- Dead signal detection: Locate unused signals carried by wires or registers
- Dead assignment detection: Identify redundant assignments
More analyses are on the way...
Lightweight
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Low Development Cost
Rapidly prototype new analyses using Qihe's infrastructure—sophisticated analyses that typically require 5,000 lines of code from scratch can be implemented in approximately 300 lines.
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Low Runtime Cost
Enabling frequent checks during the development cycle, detecting bugs in million-line designs in minutes.
Out-of-the-Box Deep Analyses
Run these analyses spanning various applications with simple commands.
Qihe handles the rest, from parsing to reporting, enabling seamless integration into your workflow.
Get Access
Qihe is now fully open source. If you encounter any issues while using Qihe, you can raise an Issue in Qihe's GitHub organization or send us an email, and we will resolve your problem as soon as possible. If you have a GitHub account, please provide the email address associated with it in the application form below so that you can receive an invitation to join Qihe's GitHub organization to access the code and recent updates.
Please note that when filling out the user information in the application form below, if you are a faculty member or student at an academic institution, please select "Academic Institution" in the "Organization Type" field and provide your academic institution email address (.edu); if you are an enterprise employee, please select "Enterprise" in the "Organization Type" field and provide your enterprise email address (academic institutions and recognized enterprise email addresses are in the preset list, and you will be automatically added to Qihe's GitHub organization after applying, while institutions not in the list will be manually reviewed); if you are an independent developer (no affiliated institution), please select "Individual" in the "Organization Type" field and provide your personal email address, and we will manually verify after receiving the application.
If you don't have a GitHub account, you can contact Qinlin Chen, Tian Tan, or Yue Li via email to obtain the code. We can send you the code via email attachment. If the application form submission fails or encounters an error, please contact us via email to let us know.