CES 2026: Taking the Lids off AMD’s Venice and MI400 SoCs
Hello you fine Internet folks, Here at CES 2026, AMD showed off their upcoming Venice series of server CPUs and their upcoming MI400 series of datacenter accelerators. AMD has talked about the specifications of both Venice and the MI400 series at their Advancing AI…
Diving into Qualcomm’s Upcoming Adreno X2 GPU with Eric Demers
Hello you fine Internet folks, Today we are talking about Qualcomm’s upcoming X2 GPU architecture with Eric Demers, Qualcomm’s GPU Team lead. We talk about the changes from the prior X1 generation of GPUs along with why some of the changes were made. Hope…
Inside Nvidia GB10’s Memory Subsystem, from the CPU Side
GB10 is a collaboration between Nvidia and Mediatek that brings Nvidia’s Blackwell architecture into an integrated GPU. GB10’s GPU has 48 Blackwell SMs, matching the RTX 5070 in core count. The CPU side has 10 Cortex X925 and 10 Cortex A725 cores and is…
SC25: The Present and Future of HPC Networking with Cornelis Networks CEO Lisa Spelman
Hello you fine Internet folks, Today we have an interview with the CEO of Cornelis Networks, Lisa Spelman, where we talk about what makes Omnipath different to other solutions on the market along with what steps has Cornelis taken in support of Ultra Ethernet.…
Nvidia’s B200: Keeping the CUDA Juggernaut Rolling ft. Verda (formerly DataCrunch)
Nvidia has dominated the GPU compute scene ever since it became mainstream. The company’s Blackwell B200 GPU is the next to take up the mantle of being the go-to compute GPU. Unlike prior generations, Blackwell can’t lean heavily on process node improvements. TSMC’s 4NP…
SC25: Estimating AMD’s Upcoming MI430X’s FP64 and the Discovery Supercomputer
Hello, you fine Internet folks, At Supercomputing 2025, EuroHPC, AMD, and Eviden announced that the second Exascale system in Europe was going to be called Alice Recoque. Powered by Eviden’s BullSequena XH3500 platform using AMD’s upcoming Instinct MI430X as most of the compute for…
Evaluating Uniform Memory Access Mode on AMD’s Turin ft. Verda (formerly DataCrunch.io)
NUMA, or Non-Uniform Memory Access, lets hardware expose affinity between cores and memory controllers to software. NUMA nodes traditionally aligned with socket boundaries, but modern server chips can subdivide a socket into multiple NUMA nodes. It’s a reflection of how non-uniform interconnects get as…
SC25: HACCing over 500 Petaflops on Frontier
Hello you fine Internet folks, Here at Supercomputing the Gordon Bell Prize is announced every year. The Gordon Bell Prize is awarded every year to recognize outstanding achievement in high-performance computing applications. One of this year’s finalist is the largest ever simulation of the…
Qualcomm’s Snapdragon X2 Elite
Hello you fine Internet folks, Last week I was in San Diego at Qualcomm’s Headquarters where Qualcomm disclosed more information about their upcoming Snapdragon X2 Elite SOC. Snapdragon X2 Elite is Qualcomm’s newest SOC for the Windows on ARM ecosystem that is designed to…
Strix Halo’s Memory Subsystem: Tackling iGPU Challenges
Editor’s Note (11/2/2025): Due to an error in moving the article over from Google Docs to Substack, the “Balancing CPU and GPU Bandwidth Demands” section was missing some Cyberpunk 2077 data. Apologizes for the mistake! AMD’s Strix Halo aspires to deliver high CPU and…
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