About

Originally from Sweden, a life-long interest in science and computers led me to a Master's degree in Applied Physics from Linköping University in 2014. Since then, I have been working with passion and hunger in the fields of FPGA and embedded software.

Alongside my professional work I am an active contributor in the open-source FPGA community. I am currently the author and maintainer of three FPGA-related open-source projects. Please see my GitHub or the project list below for details.

In my free time, I enjoy reading, exercising and being in nature. The exercise of choice depends on the season, but you will usually find me strength training, ice skating or mountain biking.

Open-source projects

hdl-modules

I am the author and maintainer of hdl-modules, a collection of reusable, high-quality, peer-reviewed VHDL building blocks. Website: https://hdl-modules.com

hdl-registers

I am the author and maintainer of hdl-registers, an HDL register code generator fast enough to run in real time. Website: https://hdl-registers.com

tsfpga

I am the author and maintainer of tsfpga, a flexible and scalable development platform for modern FPGA projects. Website: https://tsfpga.com

Professional experience

FPGA Engineer for financial trading

At IMC Trading, 2025–

Development of custom FPGA-based trading solutions.

FPGA/software development for cell therapy

At Sarcura, 2024–2025

Responsible for digital design of a product that automates CAR-T cell manufacturing for cancer care. I wrote the complete stack of FPGA (VHDL), embedded software (C++) and PC client (Python) from scratch in six months. Including a custom TCP link for device configuration, status diagnostics, and data logging/visualization.

Co-founder, FPGA expert

At Truestream, 2019–2023

An FPGA design startup I founded with some friends. I worked as an FPGA expert on some very advanced products with bleeding-edge high-speed design. Example projects from these years:

  • Lead developer for an FPGA-based ethernet switch
  • Lead developer for an FPGA-based Hi-Fi audio product
  • Lead developer for a video headend device
  • Lead developer of custom FPGA IP
I also did a lot of embedded software and PC GUI development. And, of course, a lot of other things that come with running a startup: finance, legal, sales, marketing, etc.

Freelance consultant

At Blue Steel Engineering, 2017–2019

My one-man consulting company where I provided services in FPGA/software development. Projects:

  • Embedded software for the homing system of a next-generation underwater torpedo
  • FPGA and embedded software for an industrial 3D camera, with focus on signal processing

FPGA development for self-driving cars

At Autoliv Electronics (now part of Qualcomm), 2014–2017

My first job after university. I had a variety of roles and towards the end I was the lead developer. I mainly developed VHDL cores for image processing, but I also did team leading, pre-studies, CI, etc.

Publications

Reliable FPGA CDC constraints #5: Asynchronous FIFO (article, 2024)
Reliable FPGA CDC constraints #4: Build tool settings (article, 2024)
Reliable FPGA CDC constraints #3: Pulses (article, 2024)
Reliable FPGA CDC constraints #2: Counters and FIFOs (article, 2024)
Reliable FPGA CDC constraints #1: The simple single-bit level CDC (article, 2024)

I/O timing constraints for FPGA/ASIC #6: Sink-synchronous output (article, 2025)
I/O timing constraints for FPGA/ASIC #5: System-synchronous output (article, 2025)
I/O timing constraints for FPGA/ASIC #4: Source-synchronous output (article, 2025)
I/O timing constraints for FPGA/ASIC #3: Sink-synchronous input (article, 2025)
I/O timing constraints for FPGA/ASIC #2: System-synchronous input (article, 2025)
I/O timing constraints for FPGA/ASIC #1: Source-synchronous input (article, 2025)

The many ways to mess up ready/valid handshaking (article, 2024)
Why is CDC so hard? Presentation at CERN (conference talk, 2024)
Simulate FPGA design with Vivado simulation libraries (video tutorial, 2024)

Real-time stereoscopic object tracking on FPGA using neural networks (master thesis, 2014)