freenet.support.CPUInformation

## Class IntelInfoImpl

- java.lang.Object
- - freenet.support.CPUInformation.CPUIDCPUInfo
  - - freenet.support.CPUInformation.IntelInfoImpl

- All Implemented Interfaces:
    CPUInfo, IntelCPUInfo

      class IntelInfoImpl
      extends CPUIDCPUInfo
      implements IntelCPUInfo

  Moved out of CPUID.java Ref: https://software.intel.com/en-us/articles/intel-architecture-and-processor-identification-with-cpuid-model-and-family-numbers Ref: https://en.wikipedia.org/wiki/List_of_Intel_CPU_microarchitectures Ref: https://gmplib.org/repo/gmp/file/tip/config.guess

- - ### Constructor Summary

    Constructors
    Constructor and Description
    `IntelInfoImpl()`

  - ### Method Summary

    All Methods Instance Methods Concrete Methods
    Modifier and Type | Method and Description
    --- | ---
    `String` | `getCPUModelString()` Gets the CPU model description.
    `boolean` | `IsAtomCompatible()` Supports the SSE 2 and SSE 3 instructions.
    `boolean` | `IsBroadwellCompatible()` Supports the SSE 3, 4.1, 4.2 instructions.
    `boolean` | `IsCore2Compatible()` Supports the SSE 3 instructions.
    `boolean` | `IsCoreiCompatible()` Supports the SSE 3, 4.1, 4.2 instructions.
    `boolean` | `IsHaswellCompatible()` Supports the SSE 3, 4.1, 4.2 instructions.
    `boolean` | `IsIvyCompatible()` Supports the SSE 3, 4.1, 4.2 instructions.
    `boolean` | `IsPentium2Compatible()`
    `boolean` | `IsPentium3Compatible()`
    `boolean` | `IsPentium4Compatible()` Supports the SSE 2 instructions.
    `boolean` | `IsPentiumCompatible()`
    `boolean` | `IsPentiumMCompatible()`
    `boolean` | `IsPentiumMMXCompatible()`
    `boolean` | `IsSandyCompatible()` Supports the SSE 3, 4.1, 4.2 instructions.
    `boolean` | `IsSkylakeCompatible()` Supports the AVX-512 instrutions.

    - ### Methods inherited from class freenet.support.CPUInformation.CPUIDCPUInfo

      `getVendor, hasABM, hasADX, hasAES, hasAVX, hasAVX2, hasAVX512, hasBMI1, hasBMI2, hasFMA3, hasMMX, hasMOVBE, hasSSE, hasSSE2, hasSSE3, hasSSE41, hasSSE42, hasSSE4A, hasTBM, hasX64`

    - ### Methods inherited from class java.lang.Object

      `clone, equals, finalize, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait`

    - ### Methods inherited from interface freenet.support.CPUInformation.CPUInfo

      `getVendor, hasABM, hasADX, hasAES, hasAVX, hasAVX2, hasAVX512, hasBMI1, hasBMI2, hasFMA3, hasMMX, hasMOVBE, hasSSE, hasSSE2, hasSSE3, hasSSE41, hasSSE42, hasSSE4A, hasTBM, hasX64`

- - ### Constructor Detail

    - #### IntelInfoImpl

          IntelInfoImpl()

  - ### Method Detail

    - #### getCPUModelString

          public String getCPUModelString()
                                   throws UnknownCPUException

      Description copied from interface: `CPUInfo`
      Gets the CPU model description.
      Specified by:
        `getCPUModelString` in interface `CPUInfo`
      Overrides:
        `getCPUModelString` in class `CPUIDCPUInfo`
      Returns:
        A string detailing what type of CPU that is present in the machine. I.e. 'Pentium IV' etc.
      Throws:
        `UnknownCPUException` - If for any reason the retrieval of the requested information failed. The message encapsulated in the execption indicates the cause of the failure.

    - #### IsAtomCompatible

          public boolean IsAtomCompatible()

      Description copied from interface: `IntelCPUInfo`
      Supports the SSE 2 and SSE 3 instructions. https://en.wikipedia.org/wiki/Atom_processor
      Specified by:
        `IsAtomCompatible` in interface `IntelCPUInfo`
      Returns:
        true if the CPU implements at least a Atom level instruction/feature set.

    - #### IsBroadwellCompatible

          public boolean IsBroadwellCompatible()

      Description copied from interface: `IntelCPUInfo`
      Supports the SSE 3, 4.1, 4.2 instructions. Supports the AVX 1, 2 instructions. In general, this requires 14nm or smaller process. NOT FULLY USED as of GMP 6.0. All GMP coreibwl binaries are duplicates of binaries for older technologies, so we do not distribute any. However, this is called from NativeBigInteger. Broadwell is supported in GMP 6.1 and requires the ADX instructions. Requires support for all 7 of these Corei features: FMA3 MOVBE ABM AVX2 BMI1 BMI2 ADX Pentium/Celeron Broadwell processors that do not support these instruction sets are not compatible. Those processors will be Sandy-compatible if they have AVX 1 support, and Corei-compatible if they do not.
      Specified by:
        `IsBroadwellCompatible` in interface `IntelCPUInfo`
      Returns:
        true if the CPU implements at least a Broadwell level instruction/feature set.

    - #### IsCore2Compatible

          public boolean IsCore2Compatible()

      Description copied from interface: `IntelCPUInfo`
      Supports the SSE 3 instructions.
      Specified by:
        `IsCore2Compatible` in interface `IntelCPUInfo`
      Returns:
        true if the CPU implements at least a Core2 level instruction/feature set.

    - #### IsCoreiCompatible

          public boolean IsCoreiCompatible()

      Description copied from interface: `IntelCPUInfo`
      Supports the SSE 3, 4.1, 4.2 instructions. In general, this requires 45nm or smaller process. This is the Nehalem architecture. ref: https://en.wikipedia.org/wiki/Nehalem_%28microarchitecture%29
      Specified by:
        `IsCoreiCompatible` in interface `IntelCPUInfo`
      Returns:
        true if the CPU implements at least a Corei level instruction/feature set.

    - #### IsHaswellCompatible

          public boolean IsHaswellCompatible()

      Description copied from interface: `IntelCPUInfo`
      Supports the SSE 3, 4.1, 4.2 instructions. Supports the AVX 1, 2 instructions. Supports the BMI 1, 2 instructions. WARNING - GMP 6 uses the BMI2 MULX instruction for the "coreihwl" binaries. Only Core i3/i5/i7 Haswell processors support BMI2. Requires support for all 6 of these Corei features: FMA3 MOVBE ABM AVX2 BMI1 BMI2 Pentium/Celeron Haswell processors do NOT support BMI2 and are NOT compatible. Those processors will be Sandy-compatible if they have AVX 1 support, and Corei-compatible if they do not. ref: https://software.intel.com/en-us/articles/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family ref: https://en.wikipedia.org/wiki/Haswell_%28microarchitecture%29 In general, this requires 22nm or smaller process.
      Specified by:
        `IsHaswellCompatible` in interface `IntelCPUInfo`
      Returns:
        true if the CPU implements at least a Haswell level instruction/feature set.

    - #### IsIvyCompatible

          public boolean IsIvyCompatible()

      Description copied from interface: `IntelCPUInfo`
      Supports the SSE 3, 4.1, 4.2 instructions. Supports the AVX 1 instructions. In general, this requires 22nm or smaller process. UNUSED, there is no specific GMP build for Ivy Bridge, and this is never called from NativeBigInteger. Ivy Bridge is a successor to Sandy Bridge, so use IsSandyCompatible().
      Specified by:
        `IsIvyCompatible` in interface `IntelCPUInfo`
      Returns:
        true if the CPU implements at least a IvyBridge level instruction/feature set.

    - #### IsPentium2Compatible

          public boolean IsPentium2Compatible()

      Specified by:
        `IsPentium2Compatible` in interface `IntelCPUInfo`
      Returns:
        true if the CPU implements at least the p6 instruction set (Pentium II or better). Please note that an PentimPro CPU causes/should cause this method to return false (due to that CPU using a very early implementation of the p6 instruction set. No MMX etc.)

    - #### IsPentium3Compatible

          public boolean IsPentium3Compatible()

      Specified by:
        `IsPentium3Compatible` in interface `IntelCPUInfo`
      Returns:
        true if the CPU implements at least a Pentium III level of the p6 instruction/feature set.

    - #### IsPentium4Compatible

          public boolean IsPentium4Compatible()

      Description copied from interface: `IntelCPUInfo`
      Supports the SSE 2 instructions. Does not necessarily support SSE 3. https://en.wikipedia.org/wiki/Pentium_4
      Specified by:
        `IsPentium4Compatible` in interface `IntelCPUInfo`
      Returns:
        true if the CPU implements at least a Pentium IV level instruction/feature set.

    - #### IsPentiumCompatible

          public boolean IsPentiumCompatible()

      Specified by:
        `IsPentiumCompatible` in interface `IntelCPUInfo`
      Returns:
        true if the CPU is at least a Pentium CPU.

    - #### IsPentiumMCompatible

          public boolean IsPentiumMCompatible()

      Specified by:
        `IsPentiumMCompatible` in interface `IntelCPUInfo`
      Returns:
        true if the CPU implements at least a Pentium M level instruction/feature set.

    - #### IsPentiumMMXCompatible

          public boolean IsPentiumMMXCompatible()

      Specified by:
        `IsPentiumMMXCompatible` in interface `IntelCPUInfo`
      Returns:
        true if the CPU is at least a Pentium which implements the MMX instruction/feature set.

    - #### IsSandyCompatible

          public boolean IsSandyCompatible()

      Description copied from interface: `IntelCPUInfo`
      Supports the SSE 3, 4.1, 4.2 instructions. Supports the AVX 1 instructions. In general, this requires 32nm or smaller process.
      Specified by:
        `IsSandyCompatible` in interface `IntelCPUInfo`
      Returns:
        true if the CPU implements at least a SandyBridge level instruction/feature set.

    - #### IsSkylakeCompatible

          public boolean IsSkylakeCompatible()

      Supports the AVX-512 instrutions.
      Specified by:
        `IsSkylakeCompatible` in interface `IntelCPUInfo`