Is your feature request related to a problem? Please describe.

Recently, I'm developing for some FPGA using Verilog, which is a Hardware Description Language. Common setup for Verilog uses Makefile to automate simulation and synthesize using a Verilog "compiler", e.g., iverilog or verilator. Then, the module and testbenches would be "compiled" (simulation output) to a VCD (Value Change Dump) file which is able to generate waveforms. Therefore, I'm wondering if xmake could also support similar feature out-of-box.

Describe the solution you'd like

In order to port to current architecture of xmake, I suggest taking iverilog and verilator as "compiler" chains, and treat simulation as "build" task. The simulation testbenches are the same as boilerplate code in testing in C/C++. Similarly, the Verilog code can also be build without testbenches, which is called synthesize, which produce something similar to LLVM IR for FPGAs. This is the same as building the main part of a C/C++ project. Therefore, I'm thinking of an xmake file like this:

set_languages("verilog", "system-verilog")
set_toolchains("iverilog")
add_verilog_flags("...")

target("test", {
    kind = "vcd",
    files = { "src/main.v", "tests/test.v"}
})

target("main", {
    kind = "synth",
    files = "src/main.v"
})

Describe alternatives you've considered

No response

Additional context

No response