PPC/s390: [acqrel] Added atomic acquire load and release store instructions

miladfarca · V8 LUCI CQ · commit 8b7de408d16f · 2026-01-16T16:12:26.000-08:00
Port 4029beb R=junyan1@ibm.com BUG= LOG=N Change-Id: I90b6819667613d02eefe9eaa555971fd054a2777 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/7489536 Commit-Queue: Milad Farazmand <mfarazma@ibm.com> Reviewed-by: John <junyan1@ibm.com> Cr-Commit-Position: refs/heads/main@{#104751}
diff --git a/src/wasm/baseline/ppc/liftoff-assembler-ppc-inl.h b/src/wasm/baseline/ppc/liftoff-assembler-ppc-inl.h
@@ -6,6 +6,7 @@
 #define V8_WASM_BASELINE_PPC_LIFTOFF_ASSEMBLER_PPC_INL_H_
 
 #include "src/codegen/assembler.h"
+#include "src/codegen/atomic-memory-order.h"
 #include "src/codegen/interface-descriptors-inl.h"
 #include "src/heap/mutable-page.h"
 #include "src/wasm/baseline/liftoff-assembler.h"
@@ -749,8 +750,12 @@ void LiftoffAssembler::Store(Register dst_addr, Register offset_reg,
 void LiftoffAssembler::AtomicLoad(LiftoffRegister dst, Register src_addr,
                                   Register offset_reg, uintptr_t offset_imm,
                                   LoadType type, uint32_t* protected_load_pc,
+                                  AtomicMemoryOrder memory_order,
                                   LiftoffRegList /* pinned */, bool i64_offset,
                                   Endianness /* endianness */) {
+  if (memory_order == AtomicMemoryOrder::kSeqCst) {
+    sync();
+  }
   Load(dst, src_addr, offset_reg, offset_imm, type, protected_load_pc, true,
        i64_offset);
   lwsync();
@@ -759,9 +764,17 @@ void LiftoffAssembler::AtomicLoad(LiftoffRegister dst, Register src_addr,
 void LiftoffAssembler::AtomicStore(Register dst_addr, Register offset_reg,
                                    uintptr_t offset_imm, LiftoffRegister src,
                                    StoreType type, uint32_t* protected_store_pc,
+                                   AtomicMemoryOrder memory_order,
                                    LiftoffRegList pinned, bool i64_offset,
                                    Endianness /* endianness */) {
-  lwsync();
+  DCHECK(memory_order == AtomicMemoryOrder::kSeqCst ||
+         memory_order == AtomicMemoryOrder::kAcqRel);
+
+  if (memory_order == AtomicMemoryOrder::kSeqCst) {
+    sync();
+  } else {
+    lwsync();
+  }
   Store(dst_addr, offset_reg, offset_imm, src, type, pinned, protected_store_pc,
         true, i64_offset);
   sync();
diff --git a/src/wasm/baseline/s390/liftoff-assembler-s390-inl.h b/src/wasm/baseline/s390/liftoff-assembler-s390-inl.h
@@ -6,6 +6,7 @@
 #define V8_WASM_BASELINE_S390_LIFTOFF_ASSEMBLER_S390_INL_H_
 
 #include "src/codegen/assembler.h"
+#include "src/codegen/atomic-memory-order.h"
 #include "src/codegen/interface-descriptors-inl.h"
 #include "src/heap/mutable-page.h"
 #include "src/wasm/baseline/liftoff-assembler.h"
@@ -665,6 +666,7 @@ void LiftoffAssembler::Store(Register dst_addr, Register offset_reg,
 void LiftoffAssembler::AtomicLoad(LiftoffRegister dst, Register src_addr,
                                   Register offset_reg, uintptr_t offset_imm,
                                   LoadType type, uint32_t* protected_load_pc,
+                                  AtomicMemoryOrder /* memory_order */,
                                   LiftoffRegList /* pinned */, bool i64_offset,
                                   Endianness endianness) {
   Load(dst, src_addr, offset_reg, offset_imm, type, protected_load_pc,
@@ -674,8 +676,17 @@ void LiftoffAssembler::AtomicLoad(LiftoffRegister dst, Register src_addr,
 void LiftoffAssembler::AtomicStore(Register dst_addr, Register offset_reg,
                                    uintptr_t offset_imm, LiftoffRegister src,
                                    StoreType type, uint32_t* protected_store_pc,
+                                   AtomicMemoryOrder memory_order,
                                    LiftoffRegList /* pinned */, bool i64_offset,
                                    Endianness endianness) {
+  DCHECK(memory_order == AtomicMemoryOrder::kSeqCst ||
+         memory_order == AtomicMemoryOrder::kAcqRel);
+  if (memory_order == AtomicMemoryOrder::kAcqRel) {
+    Store(dst_addr, offset_reg, offset_imm, src, type, {}, protected_store_pc,
+          true, i64_offset);
+    return;
+  }
+
 #ifdef V8_TARGET_BIG_ENDIAN
   bool reverse_bytes = endianness == LiftoffAssembler::kLittle;
 #else
