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vadimp-nvidiajwrdegoede
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platform: mellanox: Introduce support for rack manager switch
The rack switch is designed to provide high bandwidth, low latency connectivity using optical fiber as the primary interconnect. System supports 32 OSFP ports, non-blocking switching capacity of 25.6Tbps. System equipped with: - 2 replaceable power supplies (AC) with 1+1 redundancy model. - 7 replaceable fan drawers with 6+1 redundancy model. - 2 External Root of Trust or EROT (Glacier) devices for securing ASICs firmware. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Michael Shych <michaelsh@nvidia.com> Link: https://lore.kernel.org/r/20230208063331.15560-2-vadimp@nvidia.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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‎drivers/platform/x86/mlx-platform.c‎

Lines changed: 261 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -90,6 +90,12 @@
9090
#define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88
9191
#define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89
9292
#define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a
93+
#define MLXPLAT_CPLD_LPC_REG_EROT_OFFSET 0x91
94+
#define MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET 0x92
95+
#define MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET 0x93
96+
#define MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET 0x94
97+
#define MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET 0x95
98+
#define MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET 0x96
9399
#define MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET 0x9a
94100
#define MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET 0x9b
95101
#define MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET 0x9c
@@ -109,6 +115,8 @@
109115
#define MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET 0xaa
110116
#define MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET 0xab
111117
#define MLXPLAT_CPLD_LPC_REG_LC_PWR_ON 0xb2
118+
#define MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET 0xc2
119+
#define MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT 0xc3
112120
#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7
113121
#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8
114122
#define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9
@@ -214,6 +222,7 @@
214222
#define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0)
215223
#define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4)
216224
#define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0)
225+
#define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0)
217226
#define MLXPLAT_CPLD_I2C_CAP_BIT 0x04
218227
#define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5, MLXPLAT_CPLD_I2C_CAP_BIT)
219228

@@ -243,6 +252,7 @@
243252
#define MLXPLAT_CPLD_CH2_ETH_MODULAR 3
244253
#define MLXPLAT_CPLD_CH3_ETH_MODULAR 43
245254
#define MLXPLAT_CPLD_CH4_ETH_MODULAR 51
255+
#define MLXPLAT_CPLD_CH2_RACK_SWITCH 18
246256

247257
/* Number of LPC attached MUX platform devices */
248258
#define MLXPLAT_CPLD_LPC_MUX_DEVS 4
@@ -280,6 +290,9 @@
280290
/* Minimum power required for turning on Ethernet modular system (WATT) */
281291
#define MLXPLAT_CPLD_ETH_MODULAR_PWR_MIN 50
282292

293+
/* Default value for PWM control register for rack switch system */
294+
#define MLXPLAT_REGMAP_NVSWITCH_PWM_DEFAULT 0xf4
295+
283296
/* mlxplat_priv - platform private data
284297
* @pdev_i2c - i2c controller platform device
285298
* @pdev_mux - array of mux platform devices
@@ -460,6 +473,36 @@ static struct i2c_mux_reg_platform_data mlxplat_modular_mux_data[] = {
460473
},
461474
};
462475

476+
/* Platform channels for rack swicth system family */
477+
static const int mlxplat_rack_switch_channels[] = {
478+
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
479+
};
480+
481+
/* Platform rack switch mux data */
482+
static struct i2c_mux_reg_platform_data mlxplat_rack_switch_mux_data[] = {
483+
{
484+
.parent = 1,
485+
.base_nr = MLXPLAT_CPLD_CH1,
486+
.write_only = 1,
487+
.reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
488+
.reg_size = 1,
489+
.idle_in_use = 1,
490+
.values = mlxplat_rack_switch_channels,
491+
.n_values = ARRAY_SIZE(mlxplat_rack_switch_channels),
492+
},
493+
{
494+
.parent = 1,
495+
.base_nr = MLXPLAT_CPLD_CH2_RACK_SWITCH,
496+
.write_only = 1,
497+
.reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
498+
.reg_size = 1,
499+
.idle_in_use = 1,
500+
.values = mlxplat_msn21xx_channels,
501+
.n_values = ARRAY_SIZE(mlxplat_msn21xx_channels),
502+
},
503+
504+
};
505+
463506
/* Platform hotplug devices */
464507
static struct i2c_board_info mlxplat_mlxcpld_pwr[] = {
465508
{
@@ -2064,6 +2107,97 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_nvlink_blade_data = {
20642107
.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
20652108
};
20662109

2110+
/* Platform hotplug for switch systems family data */
2111+
static struct mlxreg_core_data mlxplat_mlxcpld_erot_ap_items_data[] = {
2112+
{
2113+
.label = "erot1_ap",
2114+
.reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET,
2115+
.mask = BIT(0),
2116+
.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
2117+
},
2118+
{
2119+
.label = "erot2_ap",
2120+
.reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET,
2121+
.mask = BIT(1),
2122+
.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
2123+
},
2124+
};
2125+
2126+
static struct mlxreg_core_data mlxplat_mlxcpld_erot_error_items_data[] = {
2127+
{
2128+
.label = "erot1_error",
2129+
.reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET,
2130+
.mask = BIT(0),
2131+
.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
2132+
},
2133+
{
2134+
.label = "erot2_error",
2135+
.reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET,
2136+
.mask = BIT(1),
2137+
.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
2138+
},
2139+
};
2140+
2141+
static struct mlxreg_core_item mlxplat_mlxcpld_rack_switch_items[] = {
2142+
{
2143+
.data = mlxplat_mlxcpld_ext_psu_items_data,
2144+
.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2145+
.reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
2146+
.mask = MLXPLAT_CPLD_PSU_EXT_MASK,
2147+
.capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
2148+
.count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data),
2149+
.inversed = 1,
2150+
.health = false,
2151+
},
2152+
{
2153+
.data = mlxplat_mlxcpld_ext_pwr_items_data,
2154+
.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2155+
.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
2156+
.mask = MLXPLAT_CPLD_PWR_EXT_MASK,
2157+
.capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
2158+
.count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data),
2159+
.inversed = 0,
2160+
.health = false,
2161+
},
2162+
{
2163+
.data = mlxplat_mlxcpld_default_ng_fan_items_data,
2164+
.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2165+
.reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
2166+
.mask = MLXPLAT_CPLD_FAN_NG_MASK,
2167+
.count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data),
2168+
.inversed = 1,
2169+
.health = false,
2170+
},
2171+
{
2172+
.data = mlxplat_mlxcpld_erot_ap_items_data,
2173+
.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2174+
.reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET,
2175+
.mask = MLXPLAT_CPLD_EROT_MASK,
2176+
.count = ARRAY_SIZE(mlxplat_mlxcpld_erot_ap_items_data),
2177+
.inversed = 1,
2178+
.health = false,
2179+
},
2180+
{
2181+
.data = mlxplat_mlxcpld_erot_error_items_data,
2182+
.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2183+
.reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET,
2184+
.mask = MLXPLAT_CPLD_EROT_MASK,
2185+
.count = ARRAY_SIZE(mlxplat_mlxcpld_erot_error_items_data),
2186+
.inversed = 1,
2187+
.health = false,
2188+
},
2189+
};
2190+
2191+
static
2192+
struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_rack_switch_data = {
2193+
.items = mlxplat_mlxcpld_rack_switch_items,
2194+
.counter = ARRAY_SIZE(mlxplat_mlxcpld_rack_switch_items),
2195+
.cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
2196+
.mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX,
2197+
.cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
2198+
.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
2199+
};
2200+
20672201
/* Platform led default data */
20682202
static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = {
20692203
{
@@ -2947,6 +3081,44 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
29473081
.mask = GENMASK(7, 0) & ~BIT(2),
29483082
.mode = 0200,
29493083
},
3084+
{
3085+
.label = "erot1_reset",
3086+
.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET,
3087+
.mask = GENMASK(7, 0) & ~BIT(6),
3088+
.mode = 0644,
3089+
},
3090+
{
3091+
.label = "erot2_reset",
3092+
.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET,
3093+
.mask = GENMASK(7, 0) & ~BIT(7),
3094+
.mode = 0644,
3095+
},
3096+
{
3097+
.label = "erot1_recovery",
3098+
.reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
3099+
.mask = GENMASK(7, 0) & ~BIT(6),
3100+
.mode = 0644,
3101+
},
3102+
{
3103+
.label = "erot2_recovery",
3104+
.reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
3105+
.mask = GENMASK(7, 0) & ~BIT(7),
3106+
.mode = 0644,
3107+
},
3108+
{
3109+
.label = "erot1_wp",
3110+
.reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
3111+
.mask = GENMASK(7, 0) & ~BIT(4),
3112+
.mode = 0644,
3113+
.secured = 1,
3114+
},
3115+
{
3116+
.label = "erot2_wp",
3117+
.reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
3118+
.mask = GENMASK(7, 0) & ~BIT(5),
3119+
.mode = 0644,
3120+
.secured = 1,
3121+
},
29503122
{
29513123
.label = "reset_long_pb",
29523124
.reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
@@ -3142,6 +3314,25 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
31423314
.mask = GENMASK(7, 0) & ~BIT(4),
31433315
.mode = 0644,
31443316
},
3317+
{
3318+
.label = "erot1_ap_reset",
3319+
.reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
3320+
.mask = GENMASK(7, 0) & ~BIT(0),
3321+
.mode = 0444,
3322+
},
3323+
{
3324+
.label = "erot2_ap_reset",
3325+
.reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
3326+
.mask = GENMASK(7, 0) & ~BIT(1),
3327+
.mode = 0444,
3328+
},
3329+
{
3330+
.label = "spi_chnl_select",
3331+
.reg = MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT,
3332+
.mask = GENMASK(7, 0),
3333+
.bit = 1,
3334+
.mode = 0644,
3335+
},
31453336
{
31463337
.label = "config1",
31473338
.reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET,
@@ -4257,6 +4448,10 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
42574448
case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET:
42584449
case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
42594450
case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
4451+
case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET:
4452+
case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET:
4453+
case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET:
4454+
case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET:
42604455
case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET:
42614456
case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET:
42624457
case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET:
@@ -4274,6 +4469,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
42744469
case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET:
42754470
case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET:
42764471
case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON:
4472+
case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT:
42774473
case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET:
42784474
case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET:
42794475
case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET:
@@ -4358,6 +4554,12 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
43584554
case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
43594555
case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
43604556
case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
4557+
case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET:
4558+
case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET:
4559+
case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET:
4560+
case MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET:
4561+
case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET:
4562+
case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET:
43614563
case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET:
43624564
case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET:
43634565
case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET:
@@ -4382,6 +4584,8 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
43824584
case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET:
43834585
case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET:
43844586
case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON:
4587+
case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET:
4588+
case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT:
43854589
case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET:
43864590
case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET:
43874591
case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET:
@@ -4492,6 +4696,12 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
44924696
case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
44934697
case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
44944698
case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
4699+
case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET:
4700+
case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET:
4701+
case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET:
4702+
case MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET:
4703+
case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET:
4704+
case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET:
44954705
case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET:
44964706
case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET:
44974707
case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET:
@@ -4516,6 +4726,8 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
45164726
case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET:
45174727
case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET:
45184728
case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON:
4729+
case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET:
4730+
case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT:
45194731
case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
45204732
case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
45214733
case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
@@ -4583,6 +4795,13 @@ static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = {
45834795
{ MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 },
45844796
};
45854797

4798+
static const struct reg_default mlxplat_mlxcpld_regmap_rack_switch[] = {
4799+
{ MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, MLXPLAT_REGMAP_NVSWITCH_PWM_DEFAULT },
4800+
{ MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 },
4801+
{ MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 },
4802+
{ MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 },
4803+
};
4804+
45864805
static const struct reg_default mlxplat_mlxcpld_regmap_eth_modular[] = {
45874806
{ MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 0x61 },
45884807
{ MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
@@ -4676,6 +4895,20 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng400 = {
46764895
.reg_write = mlxplat_mlxcpld_reg_write,
46774896
};
46784897

4898+
static const struct regmap_config mlxplat_mlxcpld_regmap_config_rack_switch = {
4899+
.reg_bits = 8,
4900+
.val_bits = 8,
4901+
.max_register = 255,
4902+
.cache_type = REGCACHE_FLAT,
4903+
.writeable_reg = mlxplat_mlxcpld_writeable_reg,
4904+
.readable_reg = mlxplat_mlxcpld_readable_reg,
4905+
.volatile_reg = mlxplat_mlxcpld_volatile_reg,
4906+
.reg_defaults = mlxplat_mlxcpld_regmap_rack_switch,
4907+
.num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_rack_switch),
4908+
.reg_read = mlxplat_mlxcpld_reg_read,
4909+
.reg_write = mlxplat_mlxcpld_reg_write,
4910+
};
4911+
46794912
static const struct regmap_config mlxplat_mlxcpld_regmap_config_eth_modular = {
46804913
.reg_bits = 8,
46814914
.val_bits = 8,
@@ -4957,6 +5190,27 @@ static int __init mlxplat_dmi_nvlink_blade_matched(const struct dmi_system_id *d
49575190
return 1;
49585191
}
49595192

5193+
static int __init mlxplat_dmi_rack_switch_matched(const struct dmi_system_id *dmi)
5194+
{
5195+
int i;
5196+
5197+
mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
5198+
mlxplat_mux_num = ARRAY_SIZE(mlxplat_rack_switch_mux_data);
5199+
mlxplat_mux_data = mlxplat_rack_switch_mux_data;
5200+
mlxplat_hotplug = &mlxplat_mlxcpld_rack_switch_data;
5201+
mlxplat_hotplug->deferred_nr =
5202+
mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
5203+
mlxplat_led = &mlxplat_default_ng_led_data;
5204+
mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
5205+
mlxplat_fan = &mlxplat_default_fan_data;
5206+
for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
5207+
mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
5208+
mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
5209+
mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_rack_switch;
5210+
5211+
return 1;
5212+
}
5213+
49605214
static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
49615215
{
49625216
.callback = mlxplat_dmi_default_wc_matched,
@@ -5014,6 +5268,13 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
50145268
DMI_MATCH(DMI_BOARD_NAME, "VMOD0009"),
50155269
},
50165270
},
5271+
{
5272+
.callback = mlxplat_dmi_rack_switch_matched,
5273+
.matches = {
5274+
DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"),
5275+
DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI142"),
5276+
},
5277+
},
50175278
{
50185279
.callback = mlxplat_dmi_ng400_matched,
50195280
.matches = {

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