ARM condition codes can be added to any valid ARM op-code (but not pseudo-instructions or directives). The condition code comes after any instruction suffixes.
An instruction with a condition code will be executed conditionally. Note that if the instruction is not executed there is no state change except for PC increasing to the next instruction. The non-executed instruction takes one cycle, whatever the execution time of the instruction when it is executed.
Examples
MOVEQ
STRBVC
ADDSGE
LDMFDNE
| Code | Condition | Flags Clear = 0 Set = 1 |
|---|---|---|
| EQ | equal | Z Set |
| NE | Not equal | Z Clear |
| CS/HS | Unsigned ≥ Carry Set / High or Same |
C Set |
| CC/LO | Unsigned < Carry Clear / LOw |
C Clear |
| MI | Minus (negative) | N Set |
| PL | Plus (positive or 0) | N Clear |
| VS | Signed overflow | V Set |
| VC | No signed overflow | V Clear |
| HI | Unsigned > HIgh |
C Set and Z Clear |
| LS | Unsigned ≤ Low or Same |
C Clear or Z Set |
| GE | Signed ≥ | N = V |
| LT | Signed < | N ≠ V |
| GT | Signed > | Z clear and N = V |
| LE | Signed ≤ | Z set or N ≠ V |
| AL | Always (normally omitted) | any |
| NV | Never (do not use this) | none |