base_fw: move SRAM bank details to Intel specific code#9456
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kv2019i merged 1 commit intothesofproject:mainfrom Sep 11, 2024
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The SRAM definitions like SRAM_BANK_SIZE and EBB_BANKS_IN_SEGMENT are only used in Intel specific code and not really needed in platform layer that needs to implemented by all platforms. Move these definitions to base_fw_intel.c and clean up related definitions from platform layer. Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
kv2019i
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Sep 10, 2024
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Some inline comments to explain what is removed to help with the review.
| ALIGN((HEAP_SYSTEM_S_SIZE + HEAP_SYS_RUNTIME_S_SIZE + SOF_STACK_SIZE),\ | ||
| SRAM_BANK_SIZE) | ||
| #define SOF_CORE_S_T_SIZE ((CONFIG_CORE_COUNT - 1) * SOF_CORE_S_SIZE) | ||
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This is no longer needed and needs to be removed now when SRAM_BANK_SIZE is removed.
| #define EBB_BANKS_IN_SEGMENT 32 | ||
| #define PLATFORM_HPSRAM_EBB_COUNT 32 | ||
| #define PLATFORM_LPSRAM_EBB_COUNT 1 | ||
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This is no longer needed as these definitions are only used in the Intel specific basefw code (so not needed to build for posix).
| /* data cache line alignment */ | ||
| #define PLATFORM_DCACHE_ALIGN DCACHE_LINE_SIZE | ||
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| #define SRAM_BANK_SIZE (64 * 1024) |
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This definition is in cavs25/adsp_memory.h in Zephyr, not needed here in SOF codebase. All below stuff is unused stuff that can be removed.
lgirdwood
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Sep 10, 2024
softwarecki
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Sep 10, 2024
tmleman
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Sep 10, 2024
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The SRAM definitions like SRAM_BANK_SIZE and EBB_BANKS_IN_SEGMENT are only used in Intel specific code and not really needed in platform layer that needs to implemented by all platforms. Move these definitions to base_fw_intel.c and clean up related definitions from platform layer.
Relates to #9015