This repository contains the design and implementation of a 5-stage, in-order, pipelined RISC-V processor datapath, written entirely in Verilog. The design was functionally verified in simulation and validated on a PYNQ FPGA platform.

The project focuses on core microarchitectural concepts including pipelining, hazard handling, and memory interfacing.

• Adding caches / memory levels
• Adding a proper control logic unit, instead of just pipelining all signals
• Attempting to make this superscalar & implementing a P10K based dynamic scheduling algorithm

The processor implements a classic 5-stage RISC pipeline:

1. IF – Instruction Fetch
2. ID – Instruction Decode & Register Fetch
3. EX – Execute / ALU
4. MEM – Data Memory Access
5. WB – Write Back

The datapath is fully in-order and supports parallel instruction execution via pipelining.

Key architectural features:

• Pipeline registers between all stages
• Data forwarding to resolve RAW hazards
• Hazard detection and pipeline stalling
• Separate instruction and data memories
• Synchronous register file with dual read ports

• 5-stage in-order pipelined datapath
• Data forwarding for ALU and memory dependencies
• Hazard detection with pipeline stalls
• Separate instruction and data memories
• Modular Verilog design with clear stage separation
• Comprehensive testbenches for functional verification

• Functional verification performed using xsim
• Custom testbenches written to validate:
  • Instruction execution
  • Pipeline behavior
  • Hazard detection and forwarding paths
• Hardware testing conducted on a PYNQ FPGA, validating correct execution in real hardware

• Verilog HDL
• Xilinx Vivado
• xsim for simulation
• PYNQ FPGA for hardware validation

This project emphasizes understanding, and learning how a simple datapath does things, rather than full ISA completeness.