Clocker requires a reference clock. We observe that when 100 MHz 0 dBm is applied to the SMA input the output contains high-amplitude spurious features. Increasing the input amplitude to 12 dBm resolves the problem.
Observations
(above) 100 MHz at 0 dBm from a clean RF source (Rigol DG4162).
(above) Output of Clocker with 0 dBm applied to SMA input.
(above) Output of Clocker with +12 dBm applied to SMA input.
Comment
The clock distribution chip is ADCLK950BCPZ (link). The minimum (recommended) differential clock amplitude is 0.4 Vpp (1.7 Vpp).
In [10]: Vpp = 0.4; P=Vpp**2/(850); 10np.log10(P/0.001)
Out[10]: -3.9794000867203754
In [11]: Vpp = 1.7; P=Vpp**2/(850); 10np.log10(P/0.001)
Out[11]: 8.588378514285854
Including conversion from single-ended to differential I'm surprised that this requires 12 dBm. Anyway, I've updated the wiki with a recommended input power.
Clocker requires a reference clock. We observe that when 100 MHz 0 dBm is applied to the SMA input the output contains high-amplitude spurious features. Increasing the input amplitude to 12 dBm resolves the problem.
Observations
Comment
The clock distribution chip is ADCLK950BCPZ (link). The minimum (recommended) differential clock amplitude is 0.4 Vpp (1.7 Vpp).
In [10]: Vpp = 0.4; P=Vpp**2/(850); 10np.log10(P/0.001)
Out[10]: -3.9794000867203754
In [11]: Vpp = 1.7; P=Vpp**2/(850); 10np.log10(P/0.001)
Out[11]: 8.588378514285854
Including conversion from single-ended to differential I'm surprised that this requires 12 dBm. Anyway, I've updated the wiki with a recommended input power.