Skip to content

Support GPR pair in RISC-V inline assembly #150973

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Open
taiki-e wants to merge 1 commit into
base: main
Choose a base branch
from
Open

Support GPR pair in RISC-V inline assembly #150973

taiki-e wants to merge 1 commit into from

Conversation

@taiki-e
Copy link
Member

@taiki-e taiki-e commented Jan 11, 2026

This supports RISC-V even-odd GPR pair as reg_pair class under asm_experimental_reg feature (#133416).

Both LLVM (20+) and GCC support this as R constraint, and this is useful for using AMOCAS.D on RV32 and AMOCAS.Q on RV64 instructions (currently, we need to split the value and pass it by specifying the specific register name).

Note: For now, this only implements register class and support for explicitly specifying register names is not implemented. (What name should we choose?)

Architecture Register class Target feature Allowed types
RISC-V32 reg_pair i64
RISC-V64 reg_pair i128

Refs:

r? @Amanieu

@rustbot label +A-inline-assembly +O-riscv

@rustbot rustbot added A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. S-waiting-on-author Status: This is awaiting some action (such as code changes or more information) from the author. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. A-inline-assembly Area: Inline assembly (`asm!(…)`) O-riscv Target: RISC-V architecture labels Jan 11, 2026
This was referenced Jan 11, 2026
Open
Open
@rust-log-analyzer

This comment has been minimized.

Sign in to view
@taiki-e taiki-e marked this pull request as ready for review January 13, 2026 14:09
@rustbot
Copy link
Collaborator

rustbot commented Jan 13, 2026

Some changes occurred in compiler/rustc_codegen_gcc

cc @antoyo, @GuillaumeGomez

@rustbot rustbot added S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. and removed S-waiting-on-author Status: This is awaiting some action (such as code changes or more information) from the author. labels Jan 13, 2026
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

No reviews

Assignees

@Amanieu Amanieu

Labels

A-inline-assembly Area: Inline assembly (`asm!(…)`) A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. O-riscv Target: RISC-V architecture S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

4 participants

@taiki-e @rust-log-analyzer @rustbot @Amanieu