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32-bit bootstrap enabling caches but not the MMU #84

@AntonioND

Description

@AntonioND

In the 32/bit bootstrap, caches are enabled:

mrc p15, 0, r0, c1, c0, 0 @ Read System Control Register
orr r0, r0, #(1<<2) @ cache enable
orr r0, r0, #(1<<12) @ icache enable
mcr p15, 0, r0, c1, c0, 0 @ Write System Control Register

The MMU isn't enabled, though, so it is quite useless and those lines should probably be removed.

Also, according to the kernel docs, when booting the kernel, The MMU must be off. Instruction cache may be on or off. Data cache must be off.:

https://github.com/torvalds/linux/blob/8c27ceff3604b249a9efafbd1bd8b141b79e619d/Documentation/arm/Booting#L197-L200

This affects both ARMv7 and ARMv8 in AArch32, so RPi2 and RPi3.

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