Hardware

https://github.com/sinara-hw/mirny/wiki

CPLD Gateware design

• SPI prefix-based based router (4 PLL, 4 ATT, 4 registers)
• Use only one CS, one EEM
• Independent access to RF switches as high resolution, high speed, contention-free RTIO TTL channels
• Configure RF switches via dedicated SPI register to allow saving RTIO/IO resources
• Read MUXOUT via EEM TTL RTIO (for precision timing measurements) or via SPI register
• IFC_MODE read-out
• Green LEDs driven from RF switches
• Red LEDs driven from !MUXOUT or bypassed
• Individual access to attenuators, not daisy-chained
• Fully configurable clocking, chip-enables, ATT reset, LVDS modes, MUXOUT routing modes
• Configurable mezzanine IO, bidirectional, GPIO register style, with option of routing 4 EEM IO to the mezzanine
• Documentation, flashing/deployment scripts

Status

This code and rudimentary ARTIQ coredevice support (without PLL register abstraction) are available for funding.