Commit 34322b5
[moe training] Optimize FP8 MoE backward pass: fused colwise kernel + AMD tuning (#4069)
* Add fused FP8 rowwise scale+cast Triton kernel for MoE forward pass
Adds a fused Triton kernel that replaces the 3-kernel sequence in the
forward pass of _Float8GroupedMM:
1. tensor_to_scale(A, axiswise_dim=-1)
2. A_scaled = A.to(float32) * A_scales
3. A_fp8 = to_fp8_saturated(A_scaled, fp8_dtype)
The fused kernel performs per-row absmax computation and FP8 cast in a
single kernel launch with two passes, benefiting from L2 cache reuse
on the second pass.
Benchmarked on 8x MI300X with DeepSeek-MoE-16B (EP=8, batch=4, seq=4096):
- Without fused kernel: 1,865 TPS
- With fused kernel: 2,153 TPS (~15% improvement)
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
* Add detailed comments explaining fused kernel design and usage
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
* Fix ruff formatting in float8_rowwise.py
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
* Add unit test and microbenchmark for triton_fp8_rowwise_2d_scale_and_cast
* Improve microbenchmark: add compiled-graph-unfused column
Add a third benchmark column that wraps tensor_to_scale with
torch.compiler.disable, making it opaque inside a compiled graph.
This simulates the actual MoE training context where torch.compile
cannot fuse across the tensor_to_scale boundary, leaving 3 separate
kernel launches — exactly what triton_fp8_rowwise_2d_scale_and_cast
replaces. The 'speedup vs opaque' column shows the real-world benefit.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
* benchmark: simplify to torch.compile vs triton comparison
Remove the compile+opaque column per reviewer feedback. The correct
baseline is torch.compile of the native 3-op sequence (tensor_to_scale
+ multiply + to_fp8_saturated) with fullgraph optimization, compared
directly against the fused triton kernel.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
* fix: use typing.List for Python 3.9 compatibility in benchmark
list[...] as a generic type requires Python 3.10+. Use List from typing
to support Python 3.9.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
* fix: ruff format spacing in benchmark print statement
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
* [moe training] fuse colwise FP8 quantization in backward pass
Two complementary optimizations for the MoE backward pass:
1. Add triton_fp8_per_group_colwise_scales_dual kernel: quantizes two
tensors (padded_grad_output and padded_A) in a single kernel launch.
The row-iteration loops for both tensors are merged, so each row is
visited once per pass instead of twice. When N1 == N2 (common for
square hidden dims), all blocks process both tensors simultaneously.
Reduces kernel launches by 2x and cuts per-row overhead.
2. Apply triton_fp8_rowwise_2d_scale_and_cast to grad_output rowwise
quantization in backward (for grad_A = grad_output @ B), replacing
the 3 unfused ops (tensor_to_scale + multiply + to_fp8_saturated)
with a single fused Triton kernel launch.
Together these reduce backward kernel launches from 5 per step to 2:
Before: tensor_to_scale + multiply + to_fp8_saturated (grad_A path)
+ colwise_scales(grad_output) + colwise_scales(A)
After: rowwise_2d_scale_and_cast(grad_output)
+ colwise_scales_dual(grad_output, A)
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
* [moe training][AMD] fix runtime issues and eliminate Triton autotune sync overhead
Three fixes for running FP8 MoE training on AMD MI300X:
1. Add FP8GroupedMMConfig alias in config.py
torchtitan uses the old name from the Feb 2026 refactor (commit 4a42d32).
Add a backward-compat alias so training doesn't crash on import.
2. Disable token group padding for FP8 on AMD (utils.py)
fused_pad_token_groups_cuda is not available on ROCm, so pad_token_groups()
falls back to torch_pad_token_groups which does a D2H sync (group_sizes.tolist())
that breaks torch.compile. FP8 grouped GEMM doesn't require 16-alignment padding
the way MXFP8 requires 32-alignment, so pass pad_token_groups_for_grouped_mm=False.
3. Use single fixed Triton config on AMD (jagged_float8_scales.py)
Multiple autotune configs trigger hipDeviceSynchronize for every unique
(K, N_GROUPS) shape seen during training. With ~33 unique shapes per step,
3 configs = 100 D2H syncs/step that dominate the entire backward pass.
Fix: use one fixed config (BLOCK_SIZE=128, BLOCK_SIZE_ITER=128, num_warps=8)
for all three AMD kernels (rowwise, colwise, dual colwise). This eliminates
all autotuning overhead at the cost of not finding potentially better configs
for each shape — an acceptable tradeoff on MI300X where the overhead cost
far exceeds any per-shape tuning benefit.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
* [moe training] add pad_token_groups_for_grouped_mm to Float8TrainingOpConfig
Add the pad_token_groups_for_grouped_mm field to Float8TrainingOpConfig
(defaulting to False) instead of hardcoding False in utils.py.
This matches the pattern already used by MXFP8TrainingOpConfig and lets
callers opt-in to padding when running on hardware where the CUDA padding
kernel is available. The default of False is safe on AMD/ROCm where the
torch fallback triggers a D2H sync (group_sizes.tolist()) that breaks
torch.compile.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
* [moe training][AMD] tune colwise kernel block config on MI300X
Sweep BLOCK_SIZE x BLOCK_SIZE_ITER x num_warps on representative
DeepSeek-MoE-16B backward shapes (M=16640, K=2048/5120, E=64/128).
Previous fixed config (BS=128, BSI=128, warps=8) was chosen by reasoning,
not measurement. Benchmark shows it's 2-3x slower than the optimum.
Results (MI300X, float8_e4m3fnuz):
K=2048 E=64: 128/32/8 best (200 us vs 573 us old = 2.9x)
K=5120 E=64: 32/128/4 best (492 us vs 1339 us old = 2.7x)
K=2048 E=128: 32/32/8 best (217 us vs 417 us old = 1.9x)
K=5120 E=128: 64/32/8 best (486 us vs 1005 us old = 2.1x)
Best single compromise across all shapes: BS=32, BSI=128, num_warps=4
(geomean closest to per-shape optima).
Also add bench_colwise_block_configs.py sweep benchmark.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
* [moe training] add benchmark for dual colwise FP8 scales kernel
Benchmarks triton_fp8_per_group_colwise_scales_dual vs two sequential
triton_fp8_per_group_colwise_scales calls, across representative
MoE backward shapes.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
* Remove unrelated files accidentally included in branch
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
* Fix ruff formatting in bench_colwise_block_configs.py
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
* Remove FP8GroupedMMConfig BC alias, will update torchtitan separately
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
* [moe training] replace subprocess benchmarking with standard do_bench approach
Removes multi-process BENCH_CFG mechanism in bench_colwise_block_configs.py
and replaces with standard in-process do_bench pattern consistent with other
benchmark files in this directory.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
* [moe training] Assert pad_token_groups_for_grouped_mm is False (not yet supported)
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
* [moe training] Skip distributed tests on ROCm CI (requires world_size=4)
ROCm CI has only 1 device, but test_distributed.py requires world_size=4.
Add a module-level pytest.skip for ROCm to prevent CI failures.
The ep/ and mxfp8/ distributed tests are already implicitly skipped on
ROCm via their is_sm_at_least_100() / CUDA SM100 guards.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
---------
Co-authored-by: Li <lizli102@ctr2-alola-login-01.amd.com>
Co-authored-by: Claude Opus 4.6 <noreply@anthropic.com>
Co-authored-by: Li <lizli102@ctr2-alola-ctrl-01.amd.com>1 parent d5894a7 commit 34322b5
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- benchmarks/prototype/moe_training/fp8_rowwise
- test/prototype/moe_training
- torchao/prototype/moe_training
- kernels
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