Icicle Kit Reference Design Release v2025.07

Changes since last release

New Features:

• Add support for DIE selection argument. Production silicon is now supported via the ‘MPFS250T’ argument. The Engineering silicon die ‘MPFS250T_ES’ is selected by default
• Add support for Mi-V IHC IP core version 2.0.100
• Design version can now be set using the DESIGN_VERSION argument
• Silicon signature can be set using the SILICON_SIGNATURE argument
• Add new helper function to assist with debugging sourced scripts
• Bare-metal design now has a distinct project folder – MPFS_ICICLE_MSS_BAREMETAL

Fixes and Improvements:

• PCIe: USE APB interface instead of DRI for register access
• Fix SMARTHLS argument build

Tested Libero Version

This release has been tested with Libero SoC v2024.2

Pre-built programming files

The MPFS_ICICLE_KIT_2025_07.zip (for MPFS250T) and MPFS_ICICLE_KIT_ES_2025_07.zip (for MPFS250T_ES) archives contain FlashPro Express programming files for the supported design variants.

The MPFS_ICICLE_KIT_BASE_DESIGN and MPFS_ICICLE_KIT_ES_BASE_DESIGN FlashPro Express programming files included in the zip files contain both the Libero FPGA design and the Hart Software Services v2025.07 release.
These programming files can be used to program an Icicle Kit's FPGA and eNVM without running the Libero FPGA flow or building the HSS.

Starting from this release, the MPFS-ICICLE-KIT archive contains a MPFS_ICICLE_KIT_AUTO_UPDATE asset which can be used for the Auto Update feature in the Icicle Kit with production silicon:

• The MPFS_ICICLE_KIT_AUTO_UPDATE_2025_07.job file can be used to program the golden image to the SPI flash
• The MPFS_ICICLE_KIT_AUTO_UPDATE_2025_07.spi contains the base design bitstream with a .spi file extension

For more information on how to use the Auto Update feature, please refer to the Re-programming the FPGA from Linux documentation.

Icicle Kit Reference Design Release v2025.03

Changes since last release

• Update PCI class code to ensure "lspci -v" command reports PCI type correctly
• Re-generate the MSS configuration files with the 2024.2 MSS configurator
• Remove XML generated files from the repository and include them in the release assets
• Add CoreUARTapb interrupt support and modify CoreUARTapb configuration to enable Tx and Rx FIFO
• README: Fix Libero version, typos, phrasing and added clarification for MSS_BAREMETAL argument

Tested Libero Version

This release has been tested with Libero SoC v2024.2

Pre-built programming files

The MPFS_ICICLE_BASE_DESIGN_2025_03.zip release asset contains a FlashPro Express programming file including both this Libero FPGA design and Hart Software Services release v2025.03.
This programming file can be used to program an Icicle Kit's FPGA and eNVM without having to run through the Libero FPGA flow or building the HSS.

Icicle Kit Reference Design Release v2024.09

Changes since last release

• Update CoreAXI4DMAController and LSRAM core versions

Tested Libero Version

This release has been tested with Libero SoC v2023.2

Pre-built programming files

The MPFS_ICICLE_BASE_DESIGN_2024_09.zip release asset contains a FlashPro Express programming file including both this Libero FPGA design and Hart Software Services release v2024.09.
This programming file can be used to program an Icicle Kit's FPGA and eNVM without having to run through the Libero FPGA flow or building the HSS.

Icicle Kit Reference Design Release v2024.06

Changes since last release

There are no design changes in this release. The purpose of this release is to update the Hart Software Services included in the Icicle Kit Reference Design Flash Pro Express programming file to v2024.06.

Tested Libero Version

This release has been tested with Libero SoC v2023.2

Pre-built programming files

The MPFS_ICICLE_BASE_DESIGN_2024_06.zip release asset contains a FlashPro Express programming file including both this Libero FPGA design and Hart Software Services release v2024.06.
This programming file can be used to program an Icicle Kit's FPGA and eNVM without having to run through the Libero FPGA flow or building the HSS.

Note: There are no design changes in this release; only the base design (MPFS_ICICLE_BASE_DESIGN_2024.06.zip) is included. For other argument-based designs, please refer to the v2024.02 release assets.

Icicle Kit Reference Design Release v2024.02

Changes since last release

• MSS config: Updated the tRFC value for LPDDR4 from 380ns to 280ns to match the LPDDR4 data sheet
• Regenerate XML files using Libero SoC v2023.2.

Tested Libero Version

This release has been tested with Libero SoC v2023.2

Pre-built programming files

The MPFS_ICICLE_BASE_DESIGN_2024_02.zip release asset contains a FlashPro Express programming file including both this Libero FPGA design and Hart Software Services release v2024.02.
This programming file can be used to program an Icicle Kit's FPGA and eNVM without having to run through the Libero FPGA flow or building the HSS.

Icicle Kit Reference Design Release v2023.06

Changes since last release

• Add support for the Industrial Edge demo by adding two new GPIOS for the MikroBus connector

• Change the data width used for the CoreAXI4DMAController in the AXI4Stream demo example to be 64'b from 32'b.
  This change allows the CoreAXI4DMAController to transfer data at a higher maximum rate

• Resolve a bug with the AXI Stream data generator module which was incorrectly implementing the AXI4 Stream specification

Tested Libero Version

This release has been tested with Libero SoC v2022.3

Pre-built programming files

The MPFS_ICICLE_BASE_DESIGN_2023_06.zip release asset contains a FlashPro Express programming file including both this Libero FPGA design and Hart Software Services release v2023.06.
This programming file can be used to program an Icicle Kit's FPGA and eNVM without having to run through the Libero FPGA flow or building the HSS.

Icicle Kit Reference Design Release v2023.02

Changes since last release

• Re-generate the MSS configuration file with the 2022.3 MSS configurator
• Update MSS Configuration to overlay DDR memory locations
  • The 32 bit cached, 32 bit non-cached, 38 bit cached and 38 bit non-cached DDR now point to the same physical addresses (0x0) of DDR in the Linux configuration
• Add a try error block around downloaded cores - if a core can't be downloaded, e.g. on a system with no internet access, the script will continue to run and only fail if a core isn't present in a vault.
• Use latest version of CCC SG core in Vectorblox and DRI_CCC_DEMO argument designs
• Add support for SMARTHLS argument design which allows the design and generation of a hardware module described in C++ using Microchip's SmartHLS tool
  • IMPORTANT: This flag is part of an Early Access Program for SmartHLS. If you are interested, please contact your local FAE or email us at SmartHLS@microchip.com for more details on how to enable this feature.

Tested Libero Version

This release has been tested with Libero SoC v2022.3

Pre-built programming files

The MPFS_ICICLE_BASE_DESIGN_2023_02.zip release asset contains a FlashPro Express programming file including both this Libero FPGA design and Hart Software Services release v2023.02.
This programming file can be used to program an Icicle Kit's FPGA and eNVM without having to run through the Libero FPGA flow or building the HSS.

Icicle Kit Reference Design Release v2022.10

Note: this is an interim release to support Ubuntu Server on the Icicle Kit. This release updates the Icicle kit memory map, and is not compatible with releases prior to v2023.02.

For information on how to program a preinstalled Ubuntu Server Image to the Icicle Kit, please refer to the "Ubuntu Server Image" section of our documentation on how to update a PolarFire SoC development kit.

Changes since last release

• Updated the addressing used for the AXI Address SHIM to offset addresses to 0x14_xxxx_xxxx instead of 0x10_xxxx_xxxx for PCIe transactions to use the non-cached DDR.
• Updated the provided XML SEG register configuration to overlay DDR memory locations
  • The 32 bit cached, 32 bit non-cached, 38 bit cached and 38 bit non-cached DDR now point to the same physical addresses of DDR
  • This feature will be available from the Libero v2022.3 MSS configurator
• Added a clock constraint to mark FIC clocks as asynchronous

Tested Libero version

This release has been tested with Libero SoC v2022.2

Pre-built programming files

The MPFS_ICICLE_BASE_DESIGN_2022_10.zip release asset contains a FlashPro Express programming file including both this Libero FPGA design and Hart Software Services release v2022.09 with the modified XML that is now provided.
This programming file can be used to program an Icicle Kit's FPGA and eNVM without having to run through the Libero FPGA flow or building the HSS.

Icicle Kit Reference Design Release v2022.10-rc1

This release is intended to provide support for an upcoming external software release. Please use this design file if you have been advised to, otherwise continue to use the 2022.09 release with the Yocto and Buildroot SDK releases.

Icicle Kit Reference Design Release v2022.09

Changes since last release

• Locked CCC used to generate fabric clocks to the NW PLL so the clock frequency can be read by embedded software at run time
  • Updated the FIC 3 clock frequency from 62.5MHz to 50MHz
• Memory map updates
  • Updated the base addresses of FIC 0 peripherals
  • Moved the PCIe to solely operate on in the FIC 1 domain
  • Updated the base address of FIC 3 peripherals
  • The memory map table in the readme should be consulted for the updated base addresses of all peripherals
• Wrapped components in SmartDesigns
  • FIC 0 components are now contained in a "FIC_0_PERIPHERALS" SmartDesign
  • FIC 1 components are now contained in a "FIC_1_PERIPHERALS" SmartDesign
  • FIC 3 components are now contained in a "FIC_3_PERIPHERALS" SmartDesign
  • FIC 3 address generation is contained in a "FIC_3_ADDRESS_GENERATION" SmartDesign
  • Wrapped the MSS component in a SmartDesign to contain bibufs and additional components used to interface the MSS with the fabric
  • Wrapped CoreI2C components in a SmartDesign to contain bibufs
• Updated all argument designs to support the latest base configuration
  • Removed the AXI_ADDRESS_SHIM in the "BAREMETAL" argument configuration as this is expected to be a 32 bit configuration
• Added an additional CoreI2C to interface with the "ID_SC" and "ID_SD" pins of the RPi interface to read DT overlays from eeproms on RPi hats
• Renamed the "SDIO_register" to "fabric_sd_emmc_demux_select" to match the naming convention for embedded software
• Updated the HSS_UPDATE feature to use the new hex file naming convention in the HSS
• Updated the Tcl infrastructure to use wild cards for SgCores in the design - this should allow independence from Libero versions
• Removed the initial Libero version check in the base Tcl scripts
• Updated readme and block diagrams with the latest memory map configurations
• The "VECTORBLOX" argument design is now featured in the readme as a build target to add the VectorBlox CNN to the FPGA fabric

Tested Libero version

This release has been tested with Libero SoC v2022.2

Pre-built programming files

The MPFS_ICICLE_BASE_DESIGN_2022_09.zip release asset contains a FlashPro Express programming file including both this Libero FPGA design and Hart Software Services release v2022.09.
This programming file can be used to program an Icicle Kit's FPGA and eNVM without having to run through the Libero FPGA flow or building the HSS.