Summary

• Spec v2.85.0 → v2.86.0 with new §41: canonical record of today's 4-PR session.
• Documents the 3-layer jidoka armor at the GPU-CPU dispatch boundary: visibility (fix(apr-cpu-vs-gpu-output-parity-v1): make CUDA fallback decision visible without --verbose (v1.0→v1.1, PROPOSED→ACTIVE) #1428) + drift-prevention test (test(apr-cpu-vs-gpu-output-parity-v1): drift-prevention for CUDA fallback log tag #1429) + wgpu symmetry (contract(apr-cpu-vs-gpu-output-parity-v1): v1.2.0 — FALSIFY-CPU-GPU-005 wgpu visibility + parity-gate entry #1430), all under contract apr-cpu-vs-gpu-output-parity-v1 v1.0.0 → v1.2.0 ACTIVE.
• Explicitly NOT a SHIP-007 kernel fix — §40's underlying GPU bug remains. §41 converts the failure mode from silent gibberish to loud, contracted, user-visible fallback decisions.

MODEL-1 ship % nudges 80% → 87%

Because shipping default-mode apr run users with the --no-gpu documented workaround is now jidoka-safe — the diagnostic path to that flag is automatically discoverable from any default invocation on the broken canonical 7B teacher build.

Five Whys (in spec body)

1. Why armor the dispatch boundary first? MODEL-1 is already shippable via CPU; the blocker was that users got garbage with no signal.
2. Why three layers? Each addresses a distinct regression class.
3. Why bump contract three times in one day? Each PR materially corrected the contract's claims.
4. Why not implement wgpu cosine gate today? ~100-150 LOC; bounded follow-up.
5. Why is this ship % progress, not just paperwork? §40 already concluded "MODEL-1 is shippable today via CPU path" — today's chain makes that actually true for users.

Test plan

• Spec amendment is documentation-only; no code changes
• Existing CI gates apply
• Future: when the wgpu cosine gate (FALSIFY-CPU-GPU-005 part b) lands, follow up with §42 amendment

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