Further optimize fastDepthwiseConv for RISC-V Vector.#25361
Merged
asmorkalov merged 1 commit intoopencv:4.xfrom Apr 9, 2024
Merged
Further optimize fastDepthwiseConv for RISC-V Vector.#25361asmorkalov merged 1 commit intoopencv:4.xfrom
asmorkalov merged 1 commit intoopencv:4.xfrom
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mshabunin
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Apr 9, 2024
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This patch optimize
fastDepthwiseConvin the f32 layer by using RVV Native Intrinsic.This patch was tested on QEMU using VLEN=128 and VLEN=256 (
./bin/opencv_test_dnn), both GCC (trunk) and Clang (16.0.6) are passed;On the real device (k230, VLEN=128, Clang 16.0.6), For valid test cases in
conv::Conv_Depthwise,opencv_perf_dnnshowed the average acceleration of5.74xfor strided cases (benefit from using stride load instead of buffer) and1.55xfor non-strided cases (benefit from using more vector registers, m2 -> m8).Test Result ( in descending order of acceleration ratio)
Pull Request Readiness Checklist
See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request
Patch to opencv_extra has the same branch name.