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void warpAffineBlocklineNN(int *adelta, int *bdelta, short* xy, int X0, int Y0, int bw) |
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{ |
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CALL_HAL(warpAffineBlocklineNN, cv_hal_warpAffineBlocklineNN, adelta, bdelta, xy, X0, Y0, bw); |
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const int AB_BITS = MAX(10, (int)INTER_BITS); |
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int x1 = 0; |
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#if CV_TRY_SSE4_1 |
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bool useSSE4_1 = CV_CPU_HAS_SUPPORT_SSE4_1; |
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if( useSSE4_1 ) |
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opt_SSE4_1::WarpAffineInvoker_Blockline_SSE41(adelta, bdelta, xy, X0, Y0, bw); |
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else |
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#endif |
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{ |
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#if CV_SIMD128 |
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{ |
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v_int32x4 v_X0 = v_setall_s32(X0), v_Y0 = v_setall_s32(Y0); |
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int span = VTraits<v_uint16x8>::vlanes(); |
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for( ; x1 <= bw - span; x1 += span ) |
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{ |
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v_int16x8 v_dst[2]; |
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#define CV_CONVERT_MAP(ptr,offset,shift) v_pack(v_shr<AB_BITS>(v_add(shift,v_load(ptr + offset))),\ |
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v_shr<AB_BITS>(v_add(shift,v_load(ptr + offset + 4)))) |
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v_dst[0] = CV_CONVERT_MAP(adelta, x1, v_X0); |
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v_dst[1] = CV_CONVERT_MAP(bdelta, x1, v_Y0); |
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#undef CV_CONVERT_MAP |
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v_store_interleave(xy + (x1 << 1), v_dst[0], v_dst[1]); |
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} |
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} |
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#endif |
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for( ; x1 < bw; x1++ ) |
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{ |
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int X = (X0 + adelta[x1]) >> AB_BITS; |
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int Y = (Y0 + bdelta[x1]) >> AB_BITS; |
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xy[x1*2] = saturate_cast<short>(X); |
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xy[x1*2+1] = saturate_cast<short>(Y); |
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} |
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} |
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} |