lupyuen2 · lupyuen · Jun 29, 2023 · Jun 29, 2023 · Jun 29, 2023 · Jun 29, 2023
diff --git a/arch/risc-v/src/common/riscv_hostfs.c b/arch/risc-v/src/common/riscv_hostfs.c
@@ -31,6 +31,8 @@
 #include <string.h>
 #include <syscall.h>
 #include <unistd.h>
+#include <debug.h>////
+#include <assert.h>////
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -52,6 +54,9 @@
 
 static long host_call(unsigned int nbr, void *parm, size_t size)
 {
+  _info("nbr=0x%x, parm=%p, size=%ld\n", nbr, parm, size);////
+  DEBUGPANIC();//// Semihosting not supported
+
 #ifdef CONFIG_RISCV_SEMIHOSTING_HOSTFS_CACHE_COHERENCE
   up_clean_dcache(parm, parm + size);
 #endif

diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_head.S b/arch/risc-v/src/qemu-rv/qemu_rv_head.S
@@ -40,17 +40,78 @@
   .global __start
 
 __start:
+  /* Begin Test */
+
+  /* DO NOT MODIFY. Image Header expected by Linux bootloaders.
+   *
+   * This `li` instruction has no meaningful effect except that
+   * its opcode forms the magic "MZ" signature of a PE/COFF file
+   * that is required for UEFI applications.
+   *
+   * Some bootloaders check the magic "MZ" to see if the image is a valid
+   * Linux image. But modifying the bootLoader is unnecessary unless we
+   * need to do a customized secure boot. So we just put "MZ" in the
+   * header to make the bootloader happy.
+   */
+
+  c.li    s4, -13              /* Magic Signature "MZ" (2 bytes) */
+  j       real_start           /* Jump to Kernel Start (2 bytes) */
+  .long   0                    /* Executable Code padded to 8 bytes */
+  .quad   0x200000             /* Image load offset from start of RAM */
+  /* TODO: _e_initstack - __start */
+  .quad   171644               /* Effective size of kernel image, little-endian */
+  .quad   0x0                  /* Kernel flags, little-endian */
+  .long   0x2                  /* Version of this header */
+  .long   0                    /* Reserved */
+  .quad   0                    /* Reserved */
+  .ascii  "RISCV\x00\x00\x00"  /* Magic number, "RISCV" (8 bytes) */
+  .ascii  "RSC\x05"            /* Magic number 2, "RSC\x05" (4 bytes) */
+  .long   0                    /* Reserved for PE COFF offset */
+
+real_start:
+
+  /* Load UART Base Address to Register t0 */
+  li  t0, 0x10000000
+
+  /* Load `1` to Register t1 */
+  li  t1, 0x31
+  /* Store byte from Register t1 to UART Base Address, Offset 0 */
+  sb  t1, 0(t0)
+
+  /* Load `2` to Register t1 */
+  li  t1, 0x32
+  /* Store byte from Register t1 to UART Base Address, Offset 0 */
+  sb  t1, 0(t0)
+
+  /* Load `3` to Register t1 */
+  li  t1, 0x33
+  /* Store byte from Register t1 to UART Base Address, Offset 0 */
+  sb  t1, 0(t0)
+
+  /* End Test */
 
   /* Load mhartid (cpuid) */
+  /* Previously: csrr a0, mhartid */
+
+  /* We assume that OpenSBI has passed Hart ID (value 1) in Register a0. */
+  /* But NuttX expects Hart ID to start at 0, so we subtract 1. */
+  addi a0, a0, -1
 
-  csrr a0, mhartid
+  /* Print the Hart ID */
+  addi t1, a0, 0x30
+  /* Store byte from Register t1 to UART Base Address, Offset 0 */
+  sb   t1, 0(t0)
 
   /* Set stack pointer to the idle thread stack */
 
   bnez a0, 1f
   la   sp, QEMU_RV_IDLESTACK_TOP
   j    2f
 1:
+  /* Print `4` */
+  li  t0, 0x10000000
+  li  t1, 0x34
+  sb  t1, 0(t0)
 
   /* Load the number of CPUs that the kernel supports */
 
@@ -63,10 +124,16 @@ __start:
   /* If a0 (mhartid) >= t1 (the number of CPUs), stop here */
 
   blt  a0, t1, 3f
-  csrw mie, zero
+  csrw sie, zero
+  /* Previously: csrw mie, zero */
   wfi
 
 3:
+  /* Print `5` */
+  li  t0, 0x10000000
+  li  t1, 0x35
+  sb  t1, 0(t0)
+
   /* To get g_cpu_basestack[mhartid], must get g_cpu_basestack first */
 
   la   t0, g_cpu_basestack
@@ -95,13 +162,24 @@ __start:
   add  sp, sp, t0
 
 2:
+  /* Print `6` */
+  li  t0, 0x10000000
+  li  t1, 0x36
+  sb  t1, 0(t0)
 
   /* Disable all interrupts (i.e. timer, external) in mie */
 
-	csrw	mie, zero
+  csrw	sie, zero
+  /* Previously: csrw	mie, zero */
 
   la   t0, __trap_vec
-  csrw mtvec, t0
+  csrw stvec, t0
+  /* Previously: csrw mtvec, t0 */
+
+  /* Print `7` */
+  li  t0, 0x10000000
+  li  t1, 0x37
+  sb  t1, 0(t0)
 
   /* Jump to qemu_rv_start */
 

diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_start.c b/arch/risc-v/src/qemu-rv/qemu_rv_start.c
@@ -104,6 +104,7 @@ void qemu_rv_start(int mhartid)
 {
   /* Configure FPU */
 
+  *(volatile uint8_t *)0x10000000 = 'D';////
   riscv_fpuconfig();
 
   if (mhartid > 0)
@@ -112,15 +113,19 @@ void qemu_rv_start(int mhartid)
     }
 
 #ifndef CONFIG_BUILD_KERNEL
+  *(volatile uint8_t *)0x10000000 = 'E';////
   qemu_rv_clear_bss();
 #endif
 
+  *(volatile uint8_t *)0x10000000 = 'F';////
   showprogress('A');
 
 #ifdef USE_EARLYSERIALINIT
+  *(volatile uint8_t *)0x10000000 = 'G';////
   riscv_earlyserialinit();
 #endif
 
+  *(volatile uint8_t *)0x10000000 = 'H';////
   showprogress('B');
 
   /* Do board initialization */
@@ -135,14 +140,17 @@ void qemu_rv_start(int mhartid)
 
   /* Call nx_start() */
 
+  *(volatile uint8_t *)0x10000000 = 'I';////
   nx_start();
 
 cpux:
 
 #ifdef CONFIG_SMP
+  *(volatile uint8_t *)0x10000000 = 'J';////
   riscv_cpu_boot(mhartid);
 #endif
 
+  *(volatile uint8_t *)0x10000000 = 'K';////
   while (true)
     {
       asm("WFI");
@@ -157,6 +165,8 @@ void qemu_rv_start(int mhartid)
 
 void qemu_rv_start(int mhartid)
 {
+  DEBUGASSERT(mhartid == 0); ////
+
   /* NOTE: still in M-mode */
 
   if (0 == mhartid)
@@ -171,51 +181,55 @@ void qemu_rv_start(int mhartid)
   /* Disable MMU and enable PMP */
 
   WRITE_CSR(satp, 0x0);
-  WRITE_CSR(pmpaddr0, 0x3fffffffffffffull);
-  WRITE_CSR(pmpcfg0, 0xf);
+  ////WRITE_CSR(pmpaddr0, 0x3fffffffffffffull);
+  ////WRITE_CSR(pmpcfg0, 0xf);
 
   /* Set exception and interrupt delegation for S-mode */
 
-  WRITE_CSR(medeleg, 0xffff);
-  WRITE_CSR(mideleg, 0xffff);
+  ////WRITE_CSR(medeleg, 0xffff);
+  ////WRITE_CSR(mideleg, 0xffff);
 
   /* Allow to write satp from S-mode */
 
-  CLEAR_CSR(mstatus, MSTATUS_TVM);
+  ////CLEAR_CSR(mstatus, MSTATUS_TVM);
 
   /* Set mstatus to S-mode and enable SUM */
 
-  CLEAR_CSR(mstatus, ~MSTATUS_MPP_MASK);
-  SET_CSR(mstatus, MSTATUS_MPPS | SSTATUS_SUM);
+  ////CLEAR_CSR(mstatus, ~MSTATUS_MPP_MASK);
+  ////SET_CSR(mstatus, MSTATUS_MPPS | SSTATUS_SUM);
 
   /* Set the trap vector for S-mode */
 
   WRITE_CSR(stvec, (uintptr_t)__trap_vec);
 
   /* Set the trap vector for M-mode */
 
-  WRITE_CSR(mtvec, (uintptr_t)__trap_vec_m);
+  ////WRITE_CSR(mtvec, (uintptr_t)__trap_vec_m);
 
   if (0 == mhartid)
     {
       /* Only the primary CPU needs to initialize mtimer
        * before entering to S-mode
        */
 
-      up_mtimer_initialize();
+      //// TODO
+      ////up_mtimer_initialize();
     }
 
   /* Set mepc to the entry */
 
-  WRITE_CSR(mepc, (uintptr_t)qemu_rv_start_s);
+  ////WRITE_CSR(mepc, (uintptr_t)qemu_rv_start_s);
 
   /* Set a0 to mhartid explicitly and enter to S-mode */
 
-  asm volatile (
-      "mv a0, %0 \n"
-      "mret \n"
-      :: "r" (mhartid)
-  );
+  ////asm volatile (
+  ////    "mv a0, %0 \n"
+  ////    "mret \n"
+  ////    :: "r" (mhartid)
+  ////);
+
+  //// Jump to S-Mode Init ourselves
+  qemu_rv_start_s(mhartid); ////
 }
 #endif
 

diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/knsh64/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/knsh64/defconfig
@@ -8,6 +8,7 @@
 # CONFIG_DISABLE_OS_API is not set
 # CONFIG_NSH_DISABLE_LOSMART is not set
 CONFIG_16550_ADDRWIDTH=0
+CONFIG_16550_REGINCR=4
 CONFIG_16550_UART0=y
 CONFIG_16550_UART0_BASE=0x10000000
 CONFIG_16550_UART0_CLOCK=3686400
@@ -31,9 +32,9 @@ CONFIG_ARCH_HEAP_VBASE=0xC0200000
 CONFIG_ARCH_INTERRUPTSTACK=2048
 CONFIG_ARCH_KERNEL_STACKSIZE=3072
 CONFIG_ARCH_PGPOOL_MAPPING=y
-CONFIG_ARCH_PGPOOL_PBASE=0x80400000
+CONFIG_ARCH_PGPOOL_PBASE=0x40600000
 CONFIG_ARCH_PGPOOL_SIZE=4194304
-CONFIG_ARCH_PGPOOL_VBASE=0x80400000
+CONFIG_ARCH_PGPOOL_VBASE=0x40600000
 CONFIG_ARCH_RISCV=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARCH_TEXT_NPAGES=128
@@ -44,10 +45,21 @@ CONFIG_ARCH_USE_S_MODE=y
 CONFIG_BOARD_LOOPSPERMSEC=6366
 CONFIG_BUILD_KERNEL=y
 CONFIG_DEBUG_ASSERTIONS=y
+CONFIG_DEBUG_ASSERTIONS_EXPRESSION=y
+CONFIG_DEBUG_BINFMT=y
+CONFIG_DEBUG_BINFMT_ERROR=y
+CONFIG_DEBUG_BINFMT_INFO=y
+CONFIG_DEBUG_BINFMT_WARN=y
 CONFIG_DEBUG_ERROR=y
 CONFIG_DEBUG_FEATURES=y
 CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_SCHED=y
+CONFIG_DEBUG_SCHED_ERROR=y
+CONFIG_DEBUG_SCHED_INFO=y
+CONFIG_DEBUG_SCHED_WARN=y
 CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEBUG_WARN=y
 CONFIG_DEV_ZERO=y
 CONFIG_ELF=y
 CONFIG_EXAMPLES_HELLO=m
@@ -77,7 +89,7 @@ CONFIG_NSH_FILE_APPS=y
 CONFIG_NSH_READLINE=y
 CONFIG_PATH_INITIAL="/system/bin"
 CONFIG_RAM_SIZE=1048576
-CONFIG_RAM_START=0x80100000
+CONFIG_RAM_START=0x40200000
 CONFIG_READLINE_CMD_HISTORY=y
 CONFIG_RISCV_SEMIHOSTING_HOSTFS=y
 CONFIG_RR_INTERVAL=200
@@ -88,7 +100,6 @@ CONFIG_STACK_COLORATION=y
 CONFIG_START_MONTH=12
 CONFIG_START_YEAR=2021
 CONFIG_SYMTAB_ORDEREDBYNAME=y
-CONFIG_SYSLOG_TIMESTAMP=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_SYSTEM_NSH_PROGNAME="init"
 CONFIG_TESTING_GETPRIME=y

diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/nsh64/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/nsh64/defconfig
@@ -54,7 +54,7 @@ CONFIG_NSH_SYMTAB_ARRAYNAME="g_symtab"
 CONFIG_NSH_SYMTAB_COUNTNAME="g_nsymbols"
 CONFIG_PATH_INITIAL="/system/bin"
 CONFIG_RAM_SIZE=33554432
-CONFIG_RAM_START=0x80000000
+CONFIG_RAM_START=0x40200000
 CONFIG_READLINE_CMD_HISTORY=y
 CONFIG_RISCV_SEMIHOSTING_HOSTFS=y
 CONFIG_RR_INTERVAL=200

diff --git a/boards/risc-v/qemu-rv/rv-virt/scripts/ld-kernel64.script b/boards/risc-v/qemu-rv/rv-virt/scripts/ld-kernel64.script
@@ -20,9 +20,12 @@
 
 MEMORY
 {
-    kflash (rx) : ORIGIN = 0x80000000, LENGTH = 2048K   /* w/ cache */
-    ksram (rwx) : ORIGIN = 0x80200000, LENGTH = 2048K   /* w/ cache */
-    pgram (rwx) : ORIGIN = 0x80400000, LENGTH = 4096K   /* w/ cache */
+    /* Previously 0x80000000 */
+    kflash (rx) : ORIGIN = 0x40200000, LENGTH = 2048K   /* w/ cache */
+    /* Previously 0x80200000 */
+    ksram (rwx) : ORIGIN = 0x40400000, LENGTH = 2048K   /* w/ cache */
+    /* Previously 0x80400000 */
+    pgram (rwx) : ORIGIN = 0x40600000, LENGTH = 4096K   /* w/ cache */
 }
 
 OUTPUT_ARCH("riscv")
@@ -42,7 +45,8 @@ __pgheap_size = LENGTH(pgram);
 
 SECTIONS
 {
-  . = 0x80000000;
+  /* Previously 0x80000000 */
+  . = 0x40200000;
 
   .text :
     {

diff --git a/boards/risc-v/qemu-rv/rv-virt/scripts/ld.script b/boards/risc-v/qemu-rv/rv-virt/scripts/ld.script
@@ -20,7 +20,8 @@
 
 SECTIONS
 {
-  . = 0x80000000;
+  /* Previously 0x80000000 */
+  . = 0x40200000;
 
   .text :
     {

diff --git a/sched/init/nx_bringup.c b/sched/init/nx_bringup.c
@@ -296,6 +296,7 @@ static inline void nx_start_application(void)
 
   ret = exec_spawn(CONFIG_INIT_FILEPATH, argv, NULL,
                    CONFIG_INIT_SYMTAB, CONFIG_INIT_NEXPORTS, NULL, &attr);
+  sinfo("ret=%d\n", ret);////
 #endif
   posix_spawnattr_destroy(&attr);
   DEBUGASSERT(ret > 0);

diff --git a/tools/Unix.mk b/tools/Unix.mk
@@ -250,7 +250,7 @@ tools/mkconfig$(HOSTEXEEXT):
 include/nuttx/config.h: $(TOPDIR)/.config tools/mkconfig$(HOSTEXEEXT)
 	$(Q) grep -v "CONFIG_BASE_DEFCONFIG" "$(TOPDIR)/.config" > "$(TOPDIR)/.config.tmp"
 	$(Q) if ! cmp -s "$(TOPDIR)/.config.tmp" "$(TOPDIR)/.config.orig" ; then \
-		sed -i.bak "/CONFIG_BASE_DEFCONFIG/ { /-dirty/! s/\"$$/-dirty\"/ }" "$(TOPDIR)/.config"; \
+		sed -i.bak "/CONFIG_BASE_DEFCONFIG/s/\"$$/-dirty\"/" "$(TOPDIR)/.config"; \
 	else \
 		sed -i.bak "s/-dirty//g" "$(TOPDIR)/.config"; \
 	fi