nsh> hello 3

task_spawn: name=hello entry=0x4009b4f8 file_actions=0x40a80580 attr=0x40a80588 argv=0x40a806d0

spawn_execattrs: Setting policy=2 priority=100 for pid=3

ABHello, World!!

pd_cfg2_reg=0x77711177

pd_data_reg=0x1c0000

test_render: start, channels=3

backlight_enable: start, percent=90

Configure PL10 for PWM

*0x1f02c04: clear 0x700, set 0x200

*0x1f02c04 = 0x77277

Disable R_PWM

*0x1f03800: clear 0x40, set 0x0

*0x1f03800 = 0x0

Configure R_PWM Period

*0x1f03804 = 0x4af0437

Enable R_PWM

*0x1f03800 = 0x5f

Configure PH10 for Output

*0x1c20900: clear 0x700, set 0x100

*0x1c20900 = 0x7177

Set PH10 to High

*0x1c2090c: clear 0x400, set 0x400

*0x1c2090c = 0x400

backlight_enable: end

tcon0_init: start

Configure PLL_VIDEO0

*0x1c20010 = 0x81006207

Enable LDO1 and LDO2

*0x1c20040 = 0xc00000

Configure MIPI PLL

*0x1c20040 = 0x80c0071a

Set TCON0 Clock Source to MIPI PLL

*0x1c20118 = 0x80000000

Enable TCON0 Clock

*0x1c20064 = 0x8

Deassert TCON0 Reset

*0x1c202c4 = 0x8

Disable TCON0 and Interrupts

*0x1c0c000 = 0x0

*0x1c0c004 = 0x0

*0x1c0c008 = 0x0

Enable Tristate Output

*0x1c0c08c = 0xffffffff

*0x1c0c0f4 = 0xffffffff

Set DCLK to MIPI PLL / 6

*0x1c0c044 = 0x80000006

*0x1c0c040 = 0x81000000

*0x1c0c048 = 0x2cf059f

*0x1c0c0f8 = 0x8

*0x1c0c060 = 0x10010005

Set CPU Panel Trigger

*0x1c0c160 = 0x2f02cf

*0x1c0c164 = 0x59f

*0x1c0c168 = 0x1bc2000a

Set Safe Period

*0x1c0c1f0 = 0xbb80003

Enable Output Triggers

*0x1c0c08c = 0xe0000000

Enable TCON0

*0x1c0c000: clear 0x80000000, set 0x80000000

*0x1c0c000 = 0x80000000

tcon0_init: end

display_board_init: start

Configure PD23 for Output

*0x1c20874: clear 0x70000000, set 0x10000000

*0x1c20874 = 0x17711177

Set PD23 to Low

*0x1c2087c: clear 0x800000, set 0x0

*0x1c2087c = 0x1c0000

Set DLDO1 Voltage to 3.3V

pmic_write: reg=0x15, val=0x1a

rsb_write: rt_addr=0x2d, reg_addr=0x15, value=0x1a

*0x1f0342c = 0x4e

*0x1f03430 = 0x2d0000

*0x1f03410 = 0x15

*0x1f0341c = 0x1a

*0x1f03400 = 0x80

pmic_clrsetbits: reg=0x12, clr_mask=0x0, set_mask=0x8

rsb_read: rt_addr=0x2d, reg_addr=0x12

*0x1f0342c = 0x8b

*0x1f03430 = 0x2d0000

*0x1f03410 = 0x12

*0x1f03400 = 0x80

rsb_write: rt_addr=0x2d, reg_addr=0x12, value=0xd9

*0x1f0342c = 0x4e

*0x1f03430 = 0x2d0000

*0x1f03410 = 0x12

*0x1f0341c = 0xd9

*0x1f03400 = 0x80

Set LDO Voltage to 3.3V

pmic_write: reg=0x91, val=0x1a

rsb_write: rt_addr=0x2d, reg_addr=0x91, value=0x1a

*0x1f0342c = 0x4e

*0x1f03430 = 0x2d0000

*0x1f03410 = 0x91

*0x1f0341c = 0x1a

*0x1f03400 = 0x80

Enable LDO mode on GPIO0

pmic_write: reg=0x90, val=0x3

rsb_write: rt_addr=0x2d, reg_addr=0x90, value=0x3

*0x1f0342c = 0x4e

*0x1f03430 = 0x2d0000

*0x1f03410 = 0x90

*0x1f0341c = 0x3

*0x1f03400 = 0x80

Set DLDO2 Voltage to 1.8V

pmic_write: reg=0x16, val=0xb

rsb_write: rt_addr=0x2d, reg_addr=0x16, value=0xb

*0x1f0342c = 0x4e

*0x1f03430 = 0x2d0000

*0x1f03410 = 0x16

*0x1f0341c = 0xb

*0x1f03400 = 0x80

pmic_clrsetbits: reg=0x12, clr_mask=0x0, set_mask=0x10

rsb_read: rt_addr=0x2d, reg_addr=0x12

*0x1f0342c = 0x8b

*0x1f03430 = 0x2d0000

*0x1f03410 = 0x12

*0x1f03400 = 0x80

rsb_write: rt_addr=0x2d, reg_addr=0x12, value=0xd9

*0x1f0342c = 0x4e

*0x1f03430 = 0x2d0000

*0x1f03410 = 0x12

*0x1f0341c = 0xd9

*0x1f03400 = 0x80

Wait for power supply and power-on init

display_board_init: end

enable_dsi_block: start

Enable MIPI DSI Bus

*0x1c20060: clear 0x2, set 0x2

*0x1c20060 = 0x4742

*0x1c202c0: clear 0x2, set 0x2

*0x1c202c0 = 0x4742

Enable DSI Block

*0x1ca0000 = 0x1

*0x1ca0010 = 0x30000

*0x1ca0060 = 0xa

*0x1ca0078 = 0x0

Set Instructions

*0x1ca0020 = 0x1f

*0x1ca0024 = 0x10000001

*0x1ca0028 = 0x20000010

*0x1ca002c = 0x2000000f

*0x1ca0030 = 0x30100001

*0x1ca0034 = 0x40000010

*0x1ca0038 = 0xf

*0x1ca003c = 0x5000001f

Configure Jump Instructions

*0x1ca004c = 0x560001

*0x1ca02f8 = 0xff

Set Video Start Delay

*0x1ca0014 = 0x5bc7

Set Burst

*0x1ca007c = 0x10000007

Set Instruction Loop

*0x1ca0040 = 0x30000002

*0x1ca0044 = 0x310031

*0x1ca0054 = 0x310031

Set Pixel Format

*0x1ca0090 = 0x1308703e

*0x1ca0098 = 0xffff

*0x1ca009c = 0xffffffff

*0x1ca0080 = 0x10008

Set Sync Timings

*0x1ca000c = 0x0

*0x1ca00b0 = 0x12000021

*0x1ca00b4 = 0x1000031

*0x1ca00b8 = 0x7000001

*0x1ca00bc = 0x14000011

Set Basic Size

*0x1ca0018 = 0x11000a

*0x1ca001c = 0x5cd05a0

Set Horizontal Blanking

*0x1ca00c0 = 0x9004a19

*0x1ca00c4 = 0x50b40000

*0x1ca00c8 = 0x35005419

*0x1ca00cc = 0x757a0000

*0x1ca00d0 = 0x9004a19

*0x1ca00d4 = 0x50b40000

*0x1ca00e0 = 0xc091a19

*0x1ca00e4 = 0x72bd0000

Set Vertical Blanking

*0x1ca00e8 = 0x1a000019

*0x1ca00ec = 0xffff0000

enable_dsi_block: end

dphy_enable: start

Set DSI Clock to 150 MHz

*0x1c20168 = 0x8203

Power on DPHY Tx

*0x1ca1004 = 0x10000000

*0x1ca1010 = 0xa06000e

*0x1ca1014 = 0xa033207

*0x1ca1018 = 0x1e

*0x1ca101c = 0x0

*0x1ca1020 = 0x303

Enable DPHY

*0x1ca1000 = 0x31

*0x1ca104c = 0x9f007f00

*0x1ca1050 = 0x17000000

*0x1ca105c = 0x1f01555

*0x1ca1054 = 0x2

Enable LDOR, LDOC, LDOD

*0x1ca1058 = 0x3040000

*0x1ca1058: clear 0xf8000000, set 0xf8000000

*0x1ca1058 = 0xfb040000

*0x1ca1058: clear 0x4000000, set 0x4000000

*0x1ca1058 = 0xff040000

*0x1ca1054: clear 0x10, set 0x10

*0x1ca1054 = 0x12

*0x1ca1050: clear 0x80000000, set 0x80000000

*0x1ca1050 = 0x97000000

*0x1ca1054: clear 0xf000000, set 0xf000000

*0x1ca1054 = 0xf000012

dphy_enable: end

panel_reset: start

Configure PD23 for Output

*0x1c20874: clear 0x70000000, set 0x10000000

*0x1c20874 = 0x17711177

Set PD23 to High

*0x1c2087c: clear 0x800000, set 0x800000

*0x1c2087c = 0x9c0000

wait for initialization

panel_reset: end

panel_init: start

writeDcs: len=4

b9 f1 12 83

mipi_dsi_dcs_write: channel=0, cmd=0x39, len=4

composeLongPacket: channel=0, cmd=0x39, len=4

packet: len=10

39 04 00 2c b9 f1 12 83

84 5d

*0x1ca0300: clear 0xffffffff, set 0x2c000439

*0x1ca0304: clear 0xffffffff, set 0x8312f1b9

*0x1ca0308: clear 0xffffffff, set 0x5d84

*0x1ca0200: clear 0xff, set 0x9

*0x1ca0010: clear 0x1, set 0x0

*0x1ca0010: clear 0x1, set 0x1

writeDcs: len=28

ba 33 81 05 f9 0e 0e 20

00 00 00 00 00 00 00 44

25 00 91 0a 00 00 02 4f

11 00 00 37

mipi_dsi_dcs_write: channel=0, cmd=0x39, len=28

composeLongPacket: channel=0, cmd=0x39, len=28

packet: len=34

39 1c 00 2f ba 33 81 05

f9 0e 0e 20 00 00 00 00

00 00 00 44 25 00 91 0a

00 00 02 4f 11 00 00 37

2c e2

*0x1ca0300: clear 0xffffffff, set 0x2f001c39

*0x1ca0304: clear 0xffffffff, set 0x58133ba

*0x1ca0308: clear 0xffffffff, set 0x200e0ef9

*0x1ca030c: clear 0xffffffff, set 0x0

*0x1ca0310: clear 0xffffffff, set 0x44000000

*0x1ca0314: clear 0xffffffff, set 0xa910025

*0x1ca0318: clear 0xffffffff, set 0x4f020000

*0x1ca031c: clear 0xffffffff, set 0x37000011

*0x1ca0320: clear 0xffffffff, set 0xe22c

*0x1ca0200: clear 0xff, set 0x21

*0x1ca0010: clear 0x1, set 0x0

*0x1ca0010: clear 0x1, set 0x1

writeDcs: len=5

b8 25 22 20 03

mipi_dsi_dcs_write: channel=0, cmd=0x39, len=5

composeLongPacket: channel=0, cmd=0x39, len=5

packet: len=11

39 05 00 36 b8 25 22 20

03 03 72

*0x1ca0300: clear 0xffffffff, set 0x36000539

*0x1ca0304: clear 0xffffffff, set 0x202225b8

*0x1ca0308: clear 0xffffffff, set 0x720303

*0x1ca0200: clear 0xff, set 0xa

*0x1ca0010: clear 0x1, set 0x0

*0x1ca0010: clear 0x1, set 0x1

writeDcs: len=11

b3 10 10 05 05 03 ff 00

00 00 00

mipi_dsi_dcs_write: channel=0, cmd=0x39, len=11

composeLongPacket: channel=0, cmd=0x39, len=11

packet: len=17

39 0b 00 2c b3 10 10 05

05 03 ff 00 00 00 00 6f

bc

*0x1ca0300: clear 0xffffffff, set 0x2c000b39

*0x1ca0304: clear 0xffffffff, set 0x51010b3

*0x1ca0308: clear 0xffffffff, set 0xff0305

*0x1ca030c: clear 0xffffffff, set 0x6f000000

*0x1ca0310: clear 0xffffffff, set 0xbc

*0x1ca0200: clear 0xff, set 0x10

*0x1ca0010: clear 0x1, set 0x0

*0x1ca0010: clear 0x1, set 0x1

writeDcs: len=10

c0 73 73 50 50 00 c0 08

70 00

mipi_dsi_dcs_write: channel=0, cmd=0x39, len=10

composeLongPacket: channel=0, cmd=0x39, len=10

packet: len=16

39 0a 00 36 c0 73 73 50

50 00 c0 08 70 00 1b 6a

*0x1ca0300: clear 0xffffffff, set 0x36000a39

*0x1ca0304: clear 0xffffffff, set 0x507373c0

*0x1ca0308: clear 0xffffffff, set 0x8c00050

*0x1ca030c: clear 0xffffffff, set 0x6a1b0070

*0x1ca0200: clear 0xff, set 0xf

*0x1ca0010: clear 0x1, set 0x0

*0x1ca0010: clear 0x1, set 0x1

writeDcs: len=2

bc 4e

mipi_dsi_dcs_write: channel=0, cmd=0x15, len=2

composeShortPacket: channel=0, cmd=0x15, len=2

packet: len=4

15 bc 4e 35

*0x1ca0300: clear 0xffffffff, set 0x354ebc15

*0x1ca0200: clear 0xff, set 0x3

*0x1ca0010: clear 0x1, set 0x0

*0x1ca0010: clear 0x1, set 0x1

writeDcs: len=2

cc 0b

mipi_dsi_dcs_write: channel=0, cmd=0x15, len=2

composeShortPacket: channel=0, cmd=0x15, len=2

packet: len=4

15 cc 0b 22

*0x1ca0300: clear 0xffffffff, set 0x220bcc15

*0x1ca0200: clear 0xff, set 0x3

*0x1ca0010: clear 0x1, set 0x0

*0x1ca0010: clear 0x1, set 0x1

writeDcs: len=2

b4 80

mipi_dsi_dcs_write: channel=0, cmd=0x15, len=2

composeShortPacket: channel=0, cmd=0x15, len=2

packet: len=4

15 b4 80 22

*0x1ca0300: clear 0xffffffff, set 0x2280b415

*0x1ca0200: clear 0xff, set 0x3

*0x1ca0010: clear 0x1, set 0x0

*0x1ca0010: clear 0x1, set 0x1

writeDcs: len=4

b2 f0 12 f0

mipi_dsi_dcs_write: channel=0, cmd=0x39, len=4

composeLongPacket: channel=0, cmd=0x39, len=4

packet: len=10

39 04 00 2c b2 f0 12 f0

51 86

*0x1ca0300: clear 0xffffffff, set 0x2c000439

*0x1ca0304: clear 0xffffffff, set 0xf012f0b2

*0x1ca0308: clear 0xffffffff, set 0x8651

*0x1ca0200: clear 0xff, set 0x9

*0x1ca0010: clear 0x1, set 0x0

*0x1ca0010: clear 0x1, set 0x1

writeDcs: len=15

e3 00 00 0b 0b 10 10 00

00 00 00 ff 00 c0 10

mipi_dsi_dcs_write: channel=0, cmd=0x39, len=15

composeLongPacket: channel=0, cmd=0x39, len=15

packet: len=21

39 0f 00 0f e3 00 00 0b

0b 10 10 00 00 00 00 ff

00 c0 10 36 0f

*0x1ca0300: clear 0xffffffff, set 0xf000f39

*0x1ca0304: clear 0xffffffff, set 0xb0000e3

*0x1ca0308: clear 0xffffffff, set 0x10100b

*0x1ca030c: clear 0xffffffff, set 0xff000000

*0x1ca0310: clear 0xffffffff, set 0x3610c000

*0x1ca0314: clear 0xffffffff, set 0xf

*0x1ca0200: clear 0xff, set 0x14

*0x1ca0010: clear 0x1, set 0x0

*0x1ca0010: clear 0x1, set 0x1

writeDcs: len=6

c6 01 00 ff ff 00

mipi_dsi_dcs_write: channel=0, cmd=0x39, len=6

composeLongPacket: channel=0, cmd=0x39, len=6

packet: len=12

39 06 00 30 c6 01 00 ff

ff 00 8e 25

*0x1ca0300: clear 0xffffffff, set 0x30000639

*0x1ca0304: clear 0xffffffff, set 0xff0001c6

*0x1ca0308: clear 0xffffffff, set 0x258e00ff

*0x1ca0200: clear 0xff, set 0xb

*0x1ca0010: clear 0x1, set 0x0

*0x1ca0010: clear 0x1, set 0x1

writeDcs: len=13

c1 74 00 32 32 77 f1 ff

ff cc cc 77 77

mipi_dsi_dcs_write: channel=0, cmd=0x39, len=13

composeLongPacket: channel=0, cmd=0x39, len=13

packet: len=19

39 0d 00 13 c1 74 00 32

32 77 f1 ff ff cc cc 77

77 69 e4

*0x1ca0300: clear 0xffffffff, set 0x13000d39

*0x1ca0304: clear 0xffffffff, set 0x320074c1

*0x1ca0308: clear 0xffffffff, set 0xfff17732

*0x1ca030c: clear 0xffffffff, set 0x77ccccff

*0x1ca0310: clear 0xffffffff, set 0xe46977

*0x1ca0200: clear 0xff, set 0x12

*0x1ca0010: clear 0x1, set 0x0

*0x1ca0010: clear 0x1, set 0x1

writeDcs: len=3

b5 07 07

mipi_dsi_dcs_write: channel=0, cmd=0x39, len=3

composeLongPacket: channel=0, cmd=0x39, len=3

packet: len=9

39 03 00 09 b5 07 07 7b

b3

*0x1ca0300: clear 0xffffffff, set 0x9000339

*0x1ca0304: clear 0xffffffff, set 0x7b0707b5

*0x1ca0308: clear 0xffffffff, set 0xb3

*0x1ca0200: clear 0xff, set 0x8

*0x1ca0010: clear 0x1, set 0x0

*0x1ca0010: clear 0x1, set 0x1

writeDcs: len=3

b6 2c 2c

mipi_dsi_dcs_write: channel=0, cmd=0x39, len=3

composeLongPacket: channel=0, cmd=0x39, len=3

packet: len=9

39 03 00 09 b6 2c 2c 55

04

*0x1ca0300: clear 0xffffffff, set 0x9000339

*0x1ca0304: clear 0xffffffff, set 0x552c2cb6

*0x1ca0308: clear 0xffffffff, set 0x4

*0x1ca0200: clear 0xff, set 0x8

*0x1ca0010: clear 0x1, set 0x0

*0x1ca0010: clear 0x1, set 0x1

writeDcs: len=4

bf 02 11 00

mipi_dsi_dcs_write: channel=0, cmd=0x39, len=4

composeLongPacket: channel=0, cmd=0x39, len=4

packet: len=10

39 04 00 2c bf 02 11 00

b5 e9

*0x1ca0300: clear 0xffffffff, set 0x2c000439

*0x1ca0304: clear 0xffffffff, set 0x1102bf

*0x1ca0308: clear 0xffffffff, set 0xe9b5

*0x1ca0200: clear 0xff, set 0x9

*0x1ca0010: clear 0x1, set 0x0

*0x1ca0010: clear 0x1, set 0x1

writeDcs: len=64

e9 82 10 06 05 a2 0a a5

12 31 23 37 83 04 bc 27

38 0c 00 03 00 00 00 0c

00 03 00 00 00 75 75 31

88 88 88 88 88 88 13 88

64 64 20 88 88 88 88 88

88 02 88 00 00 00 00 00

00 00 00 00 00 00 00 00

mipi_dsi_dcs_write: channel=0, cmd=0x39, len=64

composeLongPacket: channel=0, cmd=0x39, len=64

packet: len=70

39 40 00 25 e9 82 10 06

05 a2 0a a5 12 31 23 37

83 04 bc 27 38 0c 00 03

00 00 00 0c 00 03 00 00

00 75 75 31 88 88 88 88

88 88 13 88 64 64 20 88

88 88 88 88 88 02 88 00

00 00 00 00 00 00 00 00

00 00 00 00 65 03

*0x1ca0300: clear 0xffffffff, set 0x25004039

*0x1ca0304: clear 0xffffffff, set 0x61082e9

*0x1ca0308: clear 0xffffffff, set 0xa50aa205

*0x1ca030c: clear 0xffffffff, set 0x37233112

*0x1ca0310: clear 0xffffffff, set 0x27bc0483

*0x1ca0314: clear 0xffffffff, set 0x3000c38

*0x1ca0318: clear 0xffffffff, set 0xc000000

*0x1ca031c: clear 0xffffffff, set 0x300

*0x1ca0320: clear 0xffffffff, set 0x31757500

*0x1ca0324: clear 0xffffffff, set 0x88888888

*0x1ca0328: clear 0xffffffff, set 0x88138888

*0x1ca032c: clear 0xffffffff, set 0x88206464

*0x1ca0330: clear 0xffffffff, set 0x88888888

*0x1ca0334: clear 0xffffffff, set 0x880288

*0x1ca0338: clear 0xffffffff, set 0x0

*0x1ca033c: clear 0xffffffff, set 0x0

*0x1ca0340: clear 0xffffffff, set 0x0

*0x1ca0344: clear 0xffffffff, set 0x365

*0x1ca0200: clear 0xff, set 0x45

*0x1ca0010: clear 0x1, set 0x0

*0x1ca0010: clear 0x1, set 0x1

writeDcs: len=62

ea 02 21 00 00 00 00 00

00 00 00 00 00 02 46 02

88 88 88 88 88 88 64 88

13 57 13 88 88 88 88 88

88 75 88 23 14 00 00 02

00 00 00 00 00 00 00 00

00 00 00 00 00 00 00 03

0a a5 00 00 00 00

mipi_dsi_dcs_write: channel=0, cmd=0x39, len=62

composeLongPacket: channel=0, cmd=0x39, len=62

packet: len=68

39 3e 00 1a ea 02 21 00

00 00 00 00 00 00 00 00

00 02 46 02 88 88 88 88

88 88 64 88 13 57 13 88

88 88 88 88 88 75 88 23

14 00 00 02 00 00 00 00

00 00 00 00 00 00 00 00

00 00 00 03 0a a5 00 00

00 00 24 1b

*0x1ca0300: clear 0xffffffff, set 0x1a003e39

*0x1ca0304: clear 0xffffffff, set 0x2102ea

*0x1ca0308: clear 0xffffffff, set 0x0

*0x1ca030c: clear 0xffffffff, set 0x0

*0x1ca0310: clear 0xffffffff, set 0x2460200

*0x1ca0314: clear 0xffffffff, set 0x88888888

*0x1ca0318: clear 0xffffffff, set 0x88648888

*0x1ca031c: clear 0xffffffff, set 0x88135713

*0x1ca0320: clear 0xffffffff, set 0x88888888

*0x1ca0324: clear 0xffffffff, set 0x23887588

*0x1ca0328: clear 0xffffffff, set 0x2000014

*0x1ca032c: clear 0xffffffff, set 0x0

*0x1ca0330: clear 0xffffffff, set 0x0

*0x1ca0334: clear 0xffffffff, set 0x0

*0x1ca0338: clear 0xffffffff, set 0x3000000

*0x1ca033c: clear 0xffffffff, set 0xa50a

*0x1ca0340: clear 0xffffffff, set 0x1b240000

*0x1ca0200: clear 0xff, set 0x43

*0x1ca0010: clear 0x1, set 0x0

*0x1ca0010: clear 0x1, set 0x1

writeDcs: len=35

e0 00 09 0d 23 27 3c 41

35 07 0d 0e 12 13 10 12

12 18 00 09 0d 23 27 3c

41 35 07 0d 0e 12 13 10

12 12 18

mipi_dsi_dcs_write: channel=0, cmd=0x39, len=35

composeLongPacket: channel=0, cmd=0x39, len=35

packet: len=41

39 23 00 20 e0 00 09 0d

23 27 3c 41 35 07 0d 0e

12 13 10 12 12 18 00 09

0d 23 27 3c 41 35 07 0d

0e 12 13 10 12 12 18 93

bf

*0x1ca0300: clear 0xffffffff, set 0x20002339

*0x1ca0304: clear 0xffffffff, set 0xd0900e0

*0x1ca0308: clear 0xffffffff, set 0x413c2723

*0x1ca030c: clear 0xffffffff, set 0xe0d0735

*0x1ca0310: clear 0xffffffff, set 0x12101312

*0x1ca0314: clear 0xffffffff, set 0x9001812

*0x1ca0318: clear 0xffffffff, set 0x3c27230d

*0x1ca031c: clear 0xffffffff, set 0xd073541

*0x1ca0320: clear 0xffffffff, set 0x1013120e

*0x1ca0324: clear 0xffffffff, set 0x93181212

*0x1ca0328: clear 0xffffffff, set 0xbf

*0x1ca0200: clear 0xff, set 0x28

*0x1ca0010: clear 0x1, set 0x0

*0x1ca0010: clear 0x1, set 0x1

writeDcs: len=1

11

mipi_dsi_dcs_write: channel=0, cmd=0x5, len=1

composeShortPacket: channel=0, cmd=0x5, len=1

packet: len=4

05 11 00 36

*0x1ca0300: clear 0xffffffff, set 0x36001105

*0x1ca0200: clear 0xff, set 0x3

*0x1ca0010: clear 0x1, set 0x0

*0x1ca0010: clear 0x1, set 0x1

writeDcs: len=1

29

mipi_dsi_dcs_write: channel=0, cmd=0x5, len=1

composeShortPacket: channel=0, cmd=0x5, len=1

packet: len=4

05 29 00 1c

*0x1ca0300: clear 0xffffffff, set 0x1c002905

*0x1ca0200: clear 0xff, set 0x3

*0x1ca0010: clear 0x1, set 0x0

*0x1ca0010: clear 0x1, set 0x1

panel_init: end

start_dsi: start

Start HSC

*0x1ca0048 = 0xf02

Commit

*0x1ca0010: clear 0x1, set 0x1

*0x1ca0010 = 0x30001

Instruction Function Lane

*0x1ca0020: clear 0x10, set 0x0

*0x1ca0020 = 0xf

Start HSD

*0x1ca0048 = 0x63f07006

Commit

*0x1ca0010: clear 0x1, set 0x1

*0x1ca0010 = 0x30001

start_dsi: end

de2_init: start

Set High Speed SRAM to DMA Mode

*0x1c00004 = 0x0

Set Display Engine PLL to 297 MHz

*0x1c20048 = 0x81001701

Wait for Display Engine PLL to be stable

Set Special Clock to Display Engine PLL

*0x1c20104: clear 0x87000000, set 0x81000000

*0x1c20104 = 0x81000000

Enable AHB for Display Engine: De-Assert Display Engine

*0x1c202c4: clear 0x1000, set 0x1000

*0x1c202c4 = 0x1008

Enable AHB for Display Engine: Pass Display Engine

*0x1c20064: clear 0x1000, set 0x1000

*0x1c20064 = 0x1008

Enable Clock for MIXER0: SCLK Clock Pass

*0x1000000: clear 0x1, set 0x1

*0x1000000 = 0x1

Enable Clock for MIXER0: HCLK Clock Reset Off

*0x1000008: clear 0x1, set 0x1

*0x1000008 = 0x1

Enable Clock for MIXER0: HCLK Clock Pass

*0x1000004: clear 0x1, set 0x1

*0x1000004 = 0x1

Route MIXER0 to TCON0

*0x1000010: clear 0x1, set 0x0

*0x1000010 = 0x0

Clear MIXER0 Registers: GLB, BLD, OVL_V, OVL_UI

*0x1100000 = 0x0

to *0x1105fff = 0x0

Disable MIXER0 VSU

*0x1120000 = 0x0

Disable MIXER0 Undocumented

*0x1130000 = 0x0

Disable MIXER0 UI_SCALER1

*0x1140000 = 0x0

Disable MIXER0 UI_SCALER2

*0x1150000 = 0x0

Disable MIXER0 FCE

*0x11a0000 = 0x0

Disable MIXER0 BWS

*0x11a2000 = 0x0

Disable MIXER0 LTI

*0x11a4000 = 0x0

Disable MIXER0 PEAKING

*0x11a6000 = 0x0

Disable MIXER0 ASE

*0x11a8000 = 0x0

Disable MIXER0 FCC

*0x11aa000 = 0x0

Disable MIXER0 DRC

*0x11b0000 = 0x0

Enable MIXER0

*0x1100000 = 0x1

de2_init: end

renderGraphics: start

initUiBlender: start

Set Blender Background

*0x1101088 = 0xff000000

Set Blender Pre-Multiply

*0x1101084 = 0x0

initUiBlender: end

initUiChannel: start

Channel 1: Set Overlay (720 x 1440)

*0x1103000 = 0xff000405

*0x1103010 = 0x4012c000

*0x110300c = 0xb40

*0x1103004 = 0x59f02cf

*0x1103088 = 0x59f02cf

*0x1103008 = 0x0

Channel 1: Set Blender Output

*0x110108c = 0x59f02cf

*0x110000c = 0x59f02cf

Channel 1: Set Blender Input Pipe 0 (720 x 1440)

*0x1101008 = 0x59f02cf

*0x1101004 = 0xff000000

*0x110100c = 0x0

*0x1101090 = 0x3010301

Channel 1: Disable Scaler

*0x1140000 = 0x0

initUiChannel: end

initUiChannel: start

Channel 2: Set Overlay (600 x 600)

*0x1104000 = 0xff000005

*0x1104010 = 0x40521000

*0x110400c = 0x960

*0x1104004 = 0x2570257

*0x1104088 = 0x2570257

*0x1104008 = 0x0

Channel 2: Set Blender Input Pipe 1 (600 x 600)

*0x1101018 = 0x2570257

*0x1101014 = 0xff000000

*0x110101c = 0x340034

*0x1101094 = 0x3010301

Channel 2: Disable Scaler

*0x1150000 = 0x0

initUiChannel: end

initUiChannel: start

Channel 3: Set Overlay (720 x 1440)

*0x1105000 = 0x7f000005

*0x1105010 = 0x40681000

*0x110500c = 0xb40

*0x1105004 = 0x59f02cf

*0x1105088 = 0x59f02cf

*0x1105008 = 0x0

Channel 3: Set Blender Input Pipe 2 (720 x 1440)

*0x1101028 = 0x59f02cf

*0x1101024 = 0xff000000

*0x110102c = 0x0

*0x1101098 = 0x3010301

Channel 3: Disable Scaler

*0x1160000 = 0x0

initUiChannel: end

applySettings: start

Set Blender Route

*0x1101080 = 0x321

Enable Blender Pipes

*0x1101000 = 0x701

Apply Settings

*0x1100008 = 0x1

applySettings: end

renderGraphics: end

test_render: end

HELLO ZIG ON PINEPHONE!

test_zig: start

Testing Compose Short Packet (Without Parameter)...

composeShortPacket: channel=0, cmd=0x5, len=1

Result:

05 11 00 36

Testing Compose Short Packet (With Parameter)...

composeShortPacket: channel=0, cmd=0x15, len=2

Result:

15 bc 4e 35

Testing Compose Long Packet...

composeLongPacket: channel=0, cmd=0x39, len=64

Result:

39 40 00 25 e9 82 10 06

05 a2 0a a5 12 31 23 37

83 04 bc 27 38 0c 00 03

00 00 00 0c 00 03 00 00

00 75 75 31 88 88 88 88

88 88 13 88 64 64 20 88

88 88 88 88 88 02 88 00

00 00 00 00 00 00 00 00

00 00 00 00 65 03

test_zig: end