release/18.x: [CGP] Drop poison-generating flags after hoisting (#90382)#90437
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tstellar merged 1 commit intollvm:release/18.xfrom Apr 30, 2024
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release/18.x: [CGP] Drop poison-generating flags after hoisting (#90382)#90437tstellar merged 1 commit intollvm:release/18.xfrom
tstellar merged 1 commit intollvm:release/18.xfrom
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@nikic What do you think about merging this PR to the release branch? |
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@llvm/pr-subscribers-llvm-transforms Author: None (llvmbot) ChangesBackport ab12bba Requested by: @dtcxzyw Full diff: https://github.com/llvm/llvm-project/pull/90437.diff 3 Files Affected:
diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp
index 8ee1f19e083e4e..1cca56fc19cfd8 100644
--- a/llvm/lib/CodeGen/CodeGenPrepare.cpp
+++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp
@@ -8154,6 +8154,7 @@ static bool optimizeBranch(BranchInst *Branch, const TargetLowering &TLI,
IRBuilder<> Builder(Branch);
if (UI->getParent() != Branch->getParent())
UI->moveBefore(Branch);
+ UI->dropPoisonGeneratingFlags();
Value *NewCmp = Builder.CreateCmp(ICmpInst::ICMP_EQ, UI,
ConstantInt::get(UI->getType(), 0));
LLVM_DEBUG(dbgs() << "Converting " << *Cmp << "\n");
@@ -8167,6 +8168,7 @@ static bool optimizeBranch(BranchInst *Branch, const TargetLowering &TLI,
IRBuilder<> Builder(Branch);
if (UI->getParent() != Branch->getParent())
UI->moveBefore(Branch);
+ UI->dropPoisonGeneratingFlags();
Value *NewCmp = Builder.CreateCmp(Cmp->getPredicate(), UI,
ConstantInt::get(UI->getType(), 0));
LLVM_DEBUG(dbgs() << "Converting " << *Cmp << "\n");
diff --git a/llvm/test/Transforms/CodeGenPrepare/ARM/branch-on-zero.ll b/llvm/test/Transforms/CodeGenPrepare/ARM/branch-on-zero.ll
index ff5cef7e781fe6..25dfb3c53a077b 100644
--- a/llvm/test/Transforms/CodeGenPrepare/ARM/branch-on-zero.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/ARM/branch-on-zero.ll
@@ -211,6 +211,29 @@ else:
ret i32 %l
}
+define i32 @sub10_else_drop_nuw(i32 %a) {
+; CHECK-LABEL: @sub10_else_drop_nuw(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[L:%.*]] = sub i32 [[A:%.*]], 10
+; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[L]], 0
+; CHECK-NEXT: br i1 [[TMP0]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: ret i32 0
+; CHECK: else:
+; CHECK-NEXT: ret i32 [[L]]
+;
+entry:
+ %c = icmp eq i32 %a, 10
+ br i1 %c, label %then, label %else
+
+then:
+ ret i32 0
+
+else:
+ %l = sub nuw i32 %a, 10
+ ret i32 %l
+}
+
define i32 @subm10_then(i32 %a) {
; CHECK-LABEL: @subm10_then(
; CHECK-NEXT: entry:
diff --git a/llvm/test/Transforms/CodeGenPrepare/RISCV/convert-to-eqz.ll b/llvm/test/Transforms/CodeGenPrepare/RISCV/convert-to-eqz.ll
new file mode 100644
index 00000000000000..a6909d14913494
--- /dev/null
+++ b/llvm/test/Transforms/CodeGenPrepare/RISCV/convert-to-eqz.ll
@@ -0,0 +1,80 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -codegenprepare -S -mtriple=riscv64 < %s | FileCheck %s
+
+define i8 @hoist_add(i8 %x) {
+; CHECK-LABEL: define i8 @hoist_add(
+; CHECK-SAME: i8 [[X:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[INC:%.*]] = add i8 [[X]], 1
+; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i8 [[INC]], 0
+; CHECK-NEXT: br i1 [[TMP0]], label [[EXIT:%.*]], label [[IF_THEN:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: br label [[EXIT]]
+; CHECK: exit:
+; CHECK-NEXT: [[RETVAL:%.*]] = phi i8 [ [[INC]], [[IF_THEN]] ], [ -1, [[ENTRY:%.*]] ]
+; CHECK-NEXT: ret i8 [[RETVAL]]
+;
+entry:
+ %cmp = icmp eq i8 %x, -1
+ br i1 %cmp, label %exit, label %if.then
+
+if.then:
+ %inc = add nuw nsw i8 %x, 1
+ br label %exit
+
+exit:
+ %retval = phi i8 [ %inc, %if.then ], [ -1, %entry ]
+ ret i8 %retval
+}
+
+define i8 @hoist_lshr(i8 %x) {
+; CHECK-LABEL: define i8 @hoist_lshr(
+; CHECK-SAME: i8 [[X:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[INC:%.*]] = lshr i8 [[X]], 3
+; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i8 [[INC]], 0
+; CHECK-NEXT: br i1 [[TMP0]], label [[EXIT:%.*]], label [[IF_THEN:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: br label [[EXIT]]
+; CHECK: exit:
+; CHECK-NEXT: [[RETVAL:%.*]] = phi i8 [ [[INC]], [[IF_THEN]] ], [ -1, [[ENTRY:%.*]] ]
+; CHECK-NEXT: ret i8 [[RETVAL]]
+;
+entry:
+ %cmp = icmp ult i8 %x, 8
+ br i1 %cmp, label %exit, label %if.then
+
+if.then:
+ %inc = lshr exact i8 %x, 3
+ br label %exit
+
+exit:
+ %retval = phi i8 [ %inc, %if.then ], [ -1, %entry ]
+ ret i8 %retval
+}
+
+define i8 @nomove_add(i8 %x) {
+; CHECK-LABEL: define i8 @nomove_add(
+; CHECK-SAME: i8 [[X:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[INC:%.*]] = add i8 [[X]], 1
+; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i8 [[INC]], 0
+; CHECK-NEXT: br i1 [[TMP0]], label [[EXIT:%.*]], label [[IF_THEN:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: br label [[EXIT]]
+; CHECK: exit:
+; CHECK-NEXT: [[RETVAL:%.*]] = phi i8 [ [[INC]], [[IF_THEN]] ], [ -1, [[ENTRY:%.*]] ]
+; CHECK-NEXT: ret i8 [[RETVAL]]
+;
+entry:
+ %inc = add nuw nsw i8 %x, 1
+ %cmp = icmp eq i8 %x, -1
+ br i1 %cmp, label %exit, label %if.then
+
+if.then:
+ br label %exit
+
+exit:
+ %retval = phi i8 [ %inc, %if.then ], [ -1, %entry ]
+ ret i8 %retval
+}
|
See the following case: ``` define i8 @SRC1(i8 %x) { entry: %cmp = icmp eq i8 %x, -1 br i1 %cmp, label %exit, label %if.then if.then: %inc = add nuw nsw i8 %x, 1 br label %exit exit: %retval = phi i8 [ %inc, %if.then ], [ -1, %entry ] ret i8 %retval } define i8 @tgt1(i8 %x) { entry: %inc = add nuw nsw i8 %x, 1 %0 = icmp eq i8 %inc, 0 br i1 %0, label %exit, label %if.then if.then: ; preds = %entry br label %exit exit: ; preds = %if.then, %entry %retval = phi i8 [ %inc, %if.then ], [ -1, %entry ] ret i8 %retval } ``` `optimizeBranch` converts `icmp eq X, -1` into cmp to zero on RISC-V and hoists the add into the entry block. Poison-generating flags should be dropped as they don't still hold. Proof: https://alive2.llvm.org/ce/z/sP7mvK Fixes llvm#90380 (cherry picked from commit ab12bba)
Collaborator
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Hi @dtcxzyw (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. |
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Backport ab12bba
Requested by: @dtcxzyw