diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp
index 9645fb5293609..1519e9d52f8a7 100644
--- a/llvm/lib/Target/Mips/MipsFastISel.cpp
+++ b/llvm/lib/Target/Mips/MipsFastISel.cpp
@@ -74,6 +74,7 @@
 using namespace llvm;
 
 extern cl::opt<bool> EmitJalrReloc;
+extern cl::opt<bool> NoZeroDivCheck;
 
 namespace {
 
@@ -1952,8 +1953,8 @@ bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
     return false;
 
   emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
-  if (!isa<ConstantInt>(I->getOperand(1)) ||
-      dyn_cast<ConstantInt>(I->getOperand(1))->isZero()) {
+  if (!NoZeroDivCheck && (!isa<ConstantInt>(I->getOperand(1)) ||
+                          dyn_cast<ConstantInt>(I->getOperand(1))->isZero())) {
     emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
   }
 
diff --git a/llvm/test/CodeGen/Mips/divrem.ll b/llvm/test/CodeGen/Mips/divrem.ll
index a29f2793c081f..e30764fef9042 100644
--- a/llvm/test/CodeGen/Mips/divrem.ll
+++ b/llvm/test/CodeGen/Mips/divrem.ll
@@ -12,6 +12,8 @@
 ; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,NOCHECK
 ; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,NOCHECK
 
+; RUN: llc -mtriple=mipsel -mcpu=mips32 -O0 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=NOCHECK
+
 ; FileCheck Prefixes:
 ;   ALL - All targets
 ;   ACC32 - Accumulator based multiply/divide on 32-bit targets