[Reassociate] Don't reassociate vXi1 logical expressions by RKSimon · Pull Request #123329 · llvm/llvm-project

RKSimon · 2025-01-17T12:12:00Z

Extends what we already do for i1 types and don't serialize vXi1 logical expressions to improve ILP.

llvm-test-suite numbers #64840 (comment) indicate that both reassociations are a net win.

Fixes #64840
Fixes #63946

Investigation for llvm#64840

llvmbot · 2025-01-17T12:12:35Z

@llvm/pr-subscribers-llvm-transforms

Author: Simon Pilgrim (RKSimon)

Changes

Extends what we already do for i1 types and don't serialize vXi1 logical expressions to improve ILP.

llvm-test-suite numbers #64840 (comment) indicate that both reassociations are a net win.

Fixes #64840
Fixes #63946

Full diff: https://github.com/llvm/llvm-project/pull/123329.diff

2 Files Affected:

(modified) llvm/lib/Transforms/Scalar/Reassociate.cpp (+1-1)
(modified) llvm/test/Transforms/Reassociate/reassoc_bool_vec.ll (+72-71)

diff --git a/llvm/lib/Transforms/Scalar/Reassociate.cpp b/llvm/lib/Transforms/Scalar/Reassociate.cpp
index bc50f23d8eb27b..bfa30ca0a7f156 100644
--- a/llvm/lib/Transforms/Scalar/Reassociate.cpp
+++ b/llvm/lib/Transforms/Scalar/Reassociate.cpp
@@ -2180,7 +2180,7 @@ void ReassociatePass::OptimizeInst(Instruction *I) {
   // is not further optimized, it is likely to be transformed back to a
   // short-circuited form for code gen, and the source order may have been
   // optimized for the most likely conditions.
-  if (I->getType()->isIntegerTy(1))
+  if (I->getType()->isIntOrIntVectorTy(1))
     return;
 
   // If this is a bitwise or instruction of operands
diff --git a/llvm/test/Transforms/Reassociate/reassoc_bool_vec.ll b/llvm/test/Transforms/Reassociate/reassoc_bool_vec.ll
index d4aa5c507ec8be..e20b9c2c219d8e 100644
--- a/llvm/test/Transforms/Reassociate/reassoc_bool_vec.ll
+++ b/llvm/test/Transforms/Reassociate/reassoc_bool_vec.ll
@@ -4,13 +4,13 @@
 define <8 x i1> @vector0(<8 x i1> %b0, <8 x i1> %b1, <8 x i1> %b2, <8 x i1> %b3, <8 x i1> %b4, <8 x i1> %b5, <8 x i1> %b6, <8 x i1> %b7) {
 ; CHECK-LABEL: define <8 x i1> @vector0(
 ; CHECK-SAME: <8 x i1> [[B0:%.*]], <8 x i1> [[B1:%.*]], <8 x i1> [[B2:%.*]], <8 x i1> [[B3:%.*]], <8 x i1> [[B4:%.*]], <8 x i1> [[B5:%.*]], <8 x i1> [[B6:%.*]], <8 x i1> [[B7:%.*]]) {
-; CHECK-NEXT:    [[OR67:%.*]] = or <8 x i1> [[B1]], [[B0]]
-; CHECK-NEXT:    [[OR45:%.*]] = or <8 x i1> [[OR67]], [[B2]]
-; CHECK-NEXT:    [[OR4567:%.*]] = or <8 x i1> [[OR45]], [[B3]]
-; CHECK-NEXT:    [[OR23:%.*]] = or <8 x i1> [[OR4567]], [[B4]]
-; CHECK-NEXT:    [[OR01:%.*]] = or <8 x i1> [[OR23]], [[B5]]
-; CHECK-NEXT:    [[OR0123:%.*]] = or <8 x i1> [[OR01]], [[B6]]
-; CHECK-NEXT:    [[OR01234567:%.*]] = or <8 x i1> [[OR0123]], [[B7]]
+; CHECK-NEXT:    [[OR01:%.*]] = or <8 x i1> [[B0]], [[B1]]
+; CHECK-NEXT:    [[OR23:%.*]] = or <8 x i1> [[B2]], [[B3]]
+; CHECK-NEXT:    [[OR45:%.*]] = or <8 x i1> [[B4]], [[B5]]
+; CHECK-NEXT:    [[OR67:%.*]] = or <8 x i1> [[B6]], [[B7]]
+; CHECK-NEXT:    [[OR0123:%.*]] = or <8 x i1> [[OR01]], [[OR23]]
+; CHECK-NEXT:    [[OR4567:%.*]] = or <8 x i1> [[OR45]], [[OR67]]
+; CHECK-NEXT:    [[OR01234567:%.*]] = or <8 x i1> [[OR0123]], [[OR4567]]
 ; CHECK-NEXT:    ret <8 x i1> [[OR01234567]]
 ;
   %or01 = or <8 x i1> %b0, %b1
@@ -26,13 +26,13 @@ define <8 x i1> @vector0(<8 x i1> %b0, <8 x i1> %b1, <8 x i1> %b2, <8 x i1> %b3,
 define <8 x i1> @vector1(<8 x i1> %b0, <8 x i1> %b1, <8 x i1> %b2, <8 x i1> %b3, <8 x i1> %b4, <8 x i1> %b5, <8 x i1> %b6, <8 x i1> %b7) {
 ; CHECK-LABEL: define <8 x i1> @vector1(
 ; CHECK-SAME: <8 x i1> [[B0:%.*]], <8 x i1> [[B1:%.*]], <8 x i1> [[B2:%.*]], <8 x i1> [[B3:%.*]], <8 x i1> [[B4:%.*]], <8 x i1> [[B5:%.*]], <8 x i1> [[B6:%.*]], <8 x i1> [[B7:%.*]]) {
-; CHECK-NEXT:    [[OR67:%.*]] = and <8 x i1> [[B1]], [[B0]]
-; CHECK-NEXT:    [[OR45:%.*]] = and <8 x i1> [[OR67]], [[B2]]
-; CHECK-NEXT:    [[OR4567:%.*]] = and <8 x i1> [[OR45]], [[B3]]
-; CHECK-NEXT:    [[OR23:%.*]] = and <8 x i1> [[OR4567]], [[B4]]
-; CHECK-NEXT:    [[OR01:%.*]] = and <8 x i1> [[OR23]], [[B5]]
-; CHECK-NEXT:    [[OR0123:%.*]] = and <8 x i1> [[OR01]], [[B6]]
-; CHECK-NEXT:    [[OR01234567:%.*]] = and <8 x i1> [[OR0123]], [[B7]]
+; CHECK-NEXT:    [[OR01:%.*]] = and <8 x i1> [[B0]], [[B1]]
+; CHECK-NEXT:    [[OR23:%.*]] = and <8 x i1> [[B2]], [[B3]]
+; CHECK-NEXT:    [[OR45:%.*]] = and <8 x i1> [[B4]], [[B5]]
+; CHECK-NEXT:    [[OR67:%.*]] = and <8 x i1> [[B6]], [[B7]]
+; CHECK-NEXT:    [[OR0123:%.*]] = and <8 x i1> [[OR01]], [[OR23]]
+; CHECK-NEXT:    [[OR4567:%.*]] = and <8 x i1> [[OR45]], [[OR67]]
+; CHECK-NEXT:    [[OR01234567:%.*]] = and <8 x i1> [[OR0123]], [[OR4567]]
 ; CHECK-NEXT:    ret <8 x i1> [[OR01234567]]
 ;
   %or01 = and <8 x i1> %b0, %b1
@@ -48,27 +48,28 @@ define <8 x i1> @vector1(<8 x i1> %b0, <8 x i1> %b1, <8 x i1> %b2, <8 x i1> %b3,
 define <8 x i1> @vector2(<8 x i1> %a, <8 x i1> %b0, <8 x i1> %b1, <8 x i1> %b2, <8 x i1> %b3, <8 x i1> %b4, <8 x i1> %b5, <8 x i1> %b6, <8 x i1> %b7) {
 ; CHECK-LABEL: define <8 x i1> @vector2(
 ; CHECK-SAME: <8 x i1> [[A:%.*]], <8 x i1> [[B0:%.*]], <8 x i1> [[B1:%.*]], <8 x i1> [[B2:%.*]], <8 x i1> [[B3:%.*]], <8 x i1> [[B4:%.*]], <8 x i1> [[B5:%.*]], <8 x i1> [[B6:%.*]], <8 x i1> [[B7:%.*]]) {
-; CHECK-NEXT:    [[OR0:%.*]] = or <8 x i1> [[B0]], [[A]]
-; CHECK-NEXT:    [[OR1:%.*]] = or <8 x i1> [[B1]], [[A]]
-; CHECK-NEXT:    [[OR2:%.*]] = or <8 x i1> [[B2]], [[A]]
-; CHECK-NEXT:    [[OR3:%.*]] = or <8 x i1> [[B3]], [[A]]
-; CHECK-NEXT:    [[OR4:%.*]] = or <8 x i1> [[B4]], [[A]]
-; CHECK-NEXT:    [[OR5:%.*]] = or <8 x i1> [[B5]], [[A]]
-; CHECK-NEXT:    [[OR6:%.*]] = or <8 x i1> [[B6]], [[A]]
-; CHECK-NEXT:    [[OR7:%.*]] = or <8 x i1> [[B7]], [[A]]
-; CHECK-NEXT:    [[XOR2:%.*]] = xor <8 x i1> [[OR1]], [[OR0]]
-; CHECK-NEXT:    [[OR045:%.*]] = xor <8 x i1> [[XOR2]], [[OR2]]
-; CHECK-NEXT:    [[XOR3:%.*]] = xor <8 x i1> [[OR045]], [[OR3]]
-; CHECK-NEXT:    [[XOR4:%.*]] = xor <8 x i1> [[XOR3]], [[OR4]]
-; CHECK-NEXT:    [[XOR5:%.*]] = xor <8 x i1> [[XOR4]], [[OR5]]
-; CHECK-NEXT:    [[XOR6:%.*]] = xor <8 x i1> [[XOR5]], [[OR6]]
+; CHECK-NEXT:    [[OR0:%.*]] = or <8 x i1> [[A]], [[B0]]
+; CHECK-NEXT:    [[OR1:%.*]] = or <8 x i1> [[A]], [[B1]]
+; CHECK-NEXT:    [[OR2:%.*]] = or <8 x i1> [[A]], [[B2]]
+; CHECK-NEXT:    [[OR3:%.*]] = or <8 x i1> [[A]], [[B3]]
+; CHECK-NEXT:    [[OR7:%.*]] = or <8 x i1> [[A]], [[B4]]
+; CHECK-NEXT:    [[OR5:%.*]] = or <8 x i1> [[A]], [[B5]]
+; CHECK-NEXT:    [[OR6:%.*]] = or <8 x i1> [[A]], [[B6]]
+; CHECK-NEXT:    [[OR8:%.*]] = or <8 x i1> [[A]], [[B7]]
+; CHECK-NEXT:    [[OR045:%.*]] = xor <8 x i1> [[OR0]], [[OR1]]
+; CHECK-NEXT:    [[XOR2:%.*]] = xor <8 x i1> [[OR045]], [[OR2]]
+; CHECK-NEXT:    [[XOR6:%.*]] = xor <8 x i1> [[XOR2]], [[OR3]]
 ; CHECK-NEXT:    [[XOR7:%.*]] = xor <8 x i1> [[XOR6]], [[OR7]]
+; CHECK-NEXT:    [[OR023:%.*]] = xor <8 x i1> [[XOR7]], [[OR5]]
+; CHECK-NEXT:    [[XOR4:%.*]] = xor <8 x i1> [[OR023]], [[OR6]]
+; CHECK-NEXT:    [[XOR8:%.*]] = xor <8 x i1> [[XOR4]], [[OR8]]
 ; CHECK-NEXT:    [[OR4560:%.*]] = or <8 x i1> [[OR045]], [[XOR2]]
-; CHECK-NEXT:    [[OR023:%.*]] = or <8 x i1> [[OR4560]], [[XOR3]]
+; CHECK-NEXT:    [[OR23:%.*]] = or <8 x i1> [[XOR6]], [[XOR7]]
 ; CHECK-NEXT:    [[OR001:%.*]] = or <8 x i1> [[OR023]], [[XOR4]]
+; CHECK-NEXT:    [[XOR5:%.*]] = or <8 x i1> [[OR045]], [[XOR8]]
+; CHECK-NEXT:    [[OR123:%.*]] = or <8 x i1> [[OR4560]], [[OR23]]
 ; CHECK-NEXT:    [[OR0123:%.*]] = or <8 x i1> [[OR001]], [[XOR5]]
-; CHECK-NEXT:    [[OR01234567:%.*]] = or <8 x i1> [[OR0123]], [[XOR6]]
-; CHECK-NEXT:    [[OR1234567:%.*]] = or <8 x i1> [[OR01234567]], [[XOR7]]
+; CHECK-NEXT:    [[OR1234567:%.*]] = or <8 x i1> [[OR123]], [[OR0123]]
 ; CHECK-NEXT:    ret <8 x i1> [[OR1234567]]
 ;
   %or0 = or <8 x i1> %b0, %a
@@ -99,20 +100,20 @@ define <8 x i1> @vector2(<8 x i1> %a, <8 x i1> %b0, <8 x i1> %b1, <8 x i1> %b2,
 define <8 x i1> @vector3(<8 x i1> %a, <8 x i1> %b0, <8 x i1> %b1, <8 x i1> %b2, <8 x i1> %b3, <8 x i1> %b4, <8 x i1> %b5, <8 x i1> %b6, <8 x i1> %b7) {
 ; CHECK-LABEL: define <8 x i1> @vector3(
 ; CHECK-SAME: <8 x i1> [[A:%.*]], <8 x i1> [[B0:%.*]], <8 x i1> [[B1:%.*]], <8 x i1> [[B2:%.*]], <8 x i1> [[B3:%.*]], <8 x i1> [[B4:%.*]], <8 x i1> [[B5:%.*]], <8 x i1> [[B6:%.*]], <8 x i1> [[B7:%.*]]) {
-; CHECK-NEXT:    [[OR0:%.*]] = or <8 x i1> [[B0]], [[A]]
-; CHECK-NEXT:    [[OR1:%.*]] = or <8 x i1> [[B1]], [[A]]
-; CHECK-NEXT:    [[OR2:%.*]] = or <8 x i1> [[B2]], [[A]]
-; CHECK-NEXT:    [[OR3:%.*]] = or <8 x i1> [[B3]], [[A]]
-; CHECK-NEXT:    [[OR4:%.*]] = or <8 x i1> [[B4]], [[A]]
-; CHECK-NEXT:    [[OR5:%.*]] = or <8 x i1> [[B5]], [[A]]
-; CHECK-NEXT:    [[OR6:%.*]] = or <8 x i1> [[B6]], [[A]]
-; CHECK-NEXT:    [[OR7:%.*]] = or <8 x i1> [[B7]], [[A]]
+; CHECK-NEXT:    [[OR1:%.*]] = or <8 x i1> [[A]], [[B0]]
+; CHECK-NEXT:    [[OR0:%.*]] = or <8 x i1> [[A]], [[B1]]
+; CHECK-NEXT:    [[OR2:%.*]] = or <8 x i1> [[A]], [[B2]]
+; CHECK-NEXT:    [[OR4:%.*]] = or <8 x i1> [[A]], [[B3]]
+; CHECK-NEXT:    [[XOR2:%.*]] = or <8 x i1> [[A]], [[B4]]
+; CHECK-NEXT:    [[OR3:%.*]] = or <8 x i1> [[A]], [[B5]]
+; CHECK-NEXT:    [[XOR0:%.*]] = or <8 x i1> [[A]], [[B6]]
+; CHECK-NEXT:    [[OR5:%.*]] = or <8 x i1> [[A]], [[B7]]
 ; CHECK-NEXT:    [[XOR3:%.*]] = xor <8 x i1> [[OR1]], [[OR0]]
-; CHECK-NEXT:    [[XOR2:%.*]] = xor <8 x i1> [[XOR3]], [[OR2]]
+; CHECK-NEXT:    [[XOR1:%.*]] = xor <8 x i1> [[OR2]], [[OR4]]
 ; CHECK-NEXT:    [[XOR7:%.*]] = xor <8 x i1> [[XOR2]], [[OR3]]
-; CHECK-NEXT:    [[XOR0:%.*]] = xor <8 x i1> [[XOR7]], [[OR4]]
 ; CHECK-NEXT:    [[XOR4:%.*]] = xor <8 x i1> [[XOR0]], [[OR5]]
-; CHECK-NEXT:    [[XOR5:%.*]] = xor <8 x i1> [[XOR4]], [[OR6]]
+; CHECK-NEXT:    [[XOR5:%.*]] = xor <8 x i1> [[XOR3]], [[XOR1]]
+; CHECK-NEXT:    [[OR7:%.*]] = xor <8 x i1> [[XOR7]], [[XOR4]]
 ; CHECK-NEXT:    [[OR4560:%.*]] = xor <8 x i1> [[XOR5]], [[OR7]]
 ; CHECK-NEXT:    ret <8 x i1> [[OR4560]]
 ;
@@ -137,20 +138,20 @@ define <8 x i1> @vector3(<8 x i1> %a, <8 x i1> %b0, <8 x i1> %b1, <8 x i1> %b2,
 define <8 x i1> @vector4(<8 x i1> %a, <8 x i1> %b0, <8 x i1> %b1, <8 x i1> %b2, <8 x i1> %b3, <8 x i1> %b4, <8 x i1> %b5, <8 x i1> %b6, <8 x i1> %b7) {
 ; CHECK-LABEL: define <8 x i1> @vector4(
 ; CHECK-SAME: <8 x i1> [[A:%.*]], <8 x i1> [[B0:%.*]], <8 x i1> [[B1:%.*]], <8 x i1> [[B2:%.*]], <8 x i1> [[B3:%.*]], <8 x i1> [[B4:%.*]], <8 x i1> [[B5:%.*]], <8 x i1> [[B6:%.*]], <8 x i1> [[B7:%.*]]) {
-; CHECK-NEXT:    [[XOR0:%.*]] = xor <8 x i1> [[B0]], [[A]]
-; CHECK-NEXT:    [[XOR1:%.*]] = xor <8 x i1> [[B1]], [[A]]
-; CHECK-NEXT:    [[XOR2:%.*]] = xor <8 x i1> [[B2]], [[A]]
-; CHECK-NEXT:    [[XOR3:%.*]] = xor <8 x i1> [[B3]], [[A]]
-; CHECK-NEXT:    [[XOR4:%.*]] = xor <8 x i1> [[B4]], [[A]]
-; CHECK-NEXT:    [[XOR5:%.*]] = xor <8 x i1> [[B5]], [[A]]
-; CHECK-NEXT:    [[XOR6:%.*]] = xor <8 x i1> [[B6]], [[A]]
-; CHECK-NEXT:    [[XOR7:%.*]] = xor <8 x i1> [[B7]], [[A]]
+; CHECK-NEXT:    [[XOR1:%.*]] = xor <8 x i1> [[A]], [[B0]]
+; CHECK-NEXT:    [[XOR0:%.*]] = xor <8 x i1> [[A]], [[B1]]
+; CHECK-NEXT:    [[XOR2:%.*]] = xor <8 x i1> [[A]], [[B2]]
+; CHECK-NEXT:    [[XOR4:%.*]] = xor <8 x i1> [[A]], [[B3]]
+; CHECK-NEXT:    [[AND2:%.*]] = xor <8 x i1> [[A]], [[B4]]
+; CHECK-NEXT:    [[XOR3:%.*]] = xor <8 x i1> [[A]], [[B5]]
+; CHECK-NEXT:    [[AND1:%.*]] = xor <8 x i1> [[A]], [[B6]]
+; CHECK-NEXT:    [[XOR5:%.*]] = xor <8 x i1> [[A]], [[B7]]
 ; CHECK-NEXT:    [[AND3:%.*]] = and <8 x i1> [[XOR1]], [[XOR0]]
-; CHECK-NEXT:    [[AND2:%.*]] = and <8 x i1> [[AND3]], [[XOR2]]
+; CHECK-NEXT:    [[AND4:%.*]] = and <8 x i1> [[XOR2]], [[XOR4]]
 ; CHECK-NEXT:    [[OR23:%.*]] = and <8 x i1> [[AND2]], [[XOR3]]
-; CHECK-NEXT:    [[AND1:%.*]] = and <8 x i1> [[OR23]], [[XOR4]]
 ; CHECK-NEXT:    [[AND0:%.*]] = and <8 x i1> [[AND1]], [[XOR5]]
-; CHECK-NEXT:    [[OR01:%.*]] = and <8 x i1> [[AND0]], [[XOR6]]
+; CHECK-NEXT:    [[OR01:%.*]] = and <8 x i1> [[AND3]], [[AND4]]
+; CHECK-NEXT:    [[XOR7:%.*]] = and <8 x i1> [[OR23]], [[AND0]]
 ; CHECK-NEXT:    [[OR0123:%.*]] = and <8 x i1> [[OR01]], [[XOR7]]
 ; CHECK-NEXT:    ret <8 x i1> [[OR0123]]
 ;
@@ -175,29 +176,29 @@ define <8 x i1> @vector4(<8 x i1> %a, <8 x i1> %b0, <8 x i1> %b1, <8 x i1> %b2,
 define <8 x i1> @vector5(<8 x i1> %a, <8 x i1> %b0, <8 x i1> %b1, <8 x i1> %b2, <8 x i1> %b3, <8 x i1> %b4, <8 x i1> %b5, <8 x i1> %b6, <8 x i1> %b7) {
 ; CHECK-LABEL: define <8 x i1> @vector5(
 ; CHECK-SAME: <8 x i1> [[A:%.*]], <8 x i1> [[B0:%.*]], <8 x i1> [[B1:%.*]], <8 x i1> [[B2:%.*]], <8 x i1> [[B3:%.*]], <8 x i1> [[B4:%.*]], <8 x i1> [[B5:%.*]], <8 x i1> [[B6:%.*]], <8 x i1> [[B7:%.*]]) {
-; CHECK-NEXT:    [[XOR0:%.*]] = xor <8 x i1> [[B0]], [[A]]
-; CHECK-NEXT:    [[XOR1:%.*]] = xor <8 x i1> [[B1]], [[A]]
-; CHECK-NEXT:    [[XOR2:%.*]] = xor <8 x i1> [[B2]], [[A]]
-; CHECK-NEXT:    [[XOR3:%.*]] = xor <8 x i1> [[B3]], [[A]]
-; CHECK-NEXT:    [[XOR4:%.*]] = xor <8 x i1> [[B4]], [[A]]
-; CHECK-NEXT:    [[XOR5:%.*]] = xor <8 x i1> [[B5]], [[A]]
-; CHECK-NEXT:    [[XOR6:%.*]] = xor <8 x i1> [[B6]], [[A]]
-; CHECK-NEXT:    [[XOR7:%.*]] = xor <8 x i1> [[B7]], [[A]]
-; CHECK-NEXT:    [[OR3:%.*]] = or <8 x i1> [[B1]], [[B0]]
+; CHECK-NEXT:    [[OR3:%.*]] = xor <8 x i1> [[A]], [[B0]]
+; CHECK-NEXT:    [[XOR0:%.*]] = xor <8 x i1> [[A]], [[B1]]
+; CHECK-NEXT:    [[OR23:%.*]] = xor <8 x i1> [[A]], [[B2]]
+; CHECK-NEXT:    [[XOR1:%.*]] = xor <8 x i1> [[A]], [[B3]]
+; CHECK-NEXT:    [[OR0:%.*]] = xor <8 x i1> [[A]], [[B4]]
+; CHECK-NEXT:    [[XOR2:%.*]] = xor <8 x i1> [[A]], [[B5]]
+; CHECK-NEXT:    [[OR0123:%.*]] = xor <8 x i1> [[A]], [[B6]]
+; CHECK-NEXT:    [[XOR3:%.*]] = xor <8 x i1> [[A]], [[B7]]
 ; CHECK-NEXT:    [[OR2:%.*]] = or <8 x i1> [[OR3]], [[XOR0]]
-; CHECK-NEXT:    [[OR23:%.*]] = or <8 x i1> [[OR2]], [[B2]]
 ; CHECK-NEXT:    [[OR1:%.*]] = or <8 x i1> [[OR23]], [[XOR1]]
-; CHECK-NEXT:    [[OR0:%.*]] = or <8 x i1> [[OR1]], [[B3]]
 ; CHECK-NEXT:    [[OR01:%.*]] = or <8 x i1> [[OR0]], [[XOR2]]
-; CHECK-NEXT:    [[OR0123:%.*]] = or <8 x i1> [[OR01]], [[B4]]
 ; CHECK-NEXT:    [[OR7:%.*]] = or <8 x i1> [[OR0123]], [[XOR3]]
-; CHECK-NEXT:    [[OR6:%.*]] = or <8 x i1> [[OR7]], [[B5]]
-; CHECK-NEXT:    [[OR67:%.*]] = or <8 x i1> [[OR6]], [[XOR4]]
-; CHECK-NEXT:    [[OR5:%.*]] = or <8 x i1> [[OR67]], [[B6]]
-; CHECK-NEXT:    [[OR4:%.*]] = or <8 x i1> [[OR5]], [[XOR5]]
-; CHECK-NEXT:    [[OR45:%.*]] = or <8 x i1> [[OR4]], [[B7]]
+; CHECK-NEXT:    [[OR45:%.*]] = or <8 x i1> [[B0]], [[B1]]
+; CHECK-NEXT:    [[XOR6:%.*]] = or <8 x i1> [[B2]], [[B3]]
+; CHECK-NEXT:    [[OR6:%.*]] = or <8 x i1> [[B4]], [[B5]]
+; CHECK-NEXT:    [[OR8:%.*]] = or <8 x i1> [[B6]], [[B7]]
+; CHECK-NEXT:    [[OR4:%.*]] = or <8 x i1> [[OR2]], [[OR1]]
+; CHECK-NEXT:    [[OR24:%.*]] = or <8 x i1> [[OR01]], [[OR7]]
 ; CHECK-NEXT:    [[OR4567:%.*]] = or <8 x i1> [[OR45]], [[XOR6]]
-; CHECK-NEXT:    [[OR01234567:%.*]] = or <8 x i1> [[OR4567]], [[XOR7]]
+; CHECK-NEXT:    [[OR67:%.*]] = or <8 x i1> [[OR6]], [[OR8]]
+; CHECK-NEXT:    [[OR123:%.*]] = or <8 x i1> [[OR4]], [[OR24]]
+; CHECK-NEXT:    [[OR4568:%.*]] = or <8 x i1> [[OR4567]], [[OR67]]
+; CHECK-NEXT:    [[OR01234567:%.*]] = or <8 x i1> [[OR4568]], [[OR123]]
 ; CHECK-NEXT:    ret <8 x i1> [[OR01234567]]
 ;
   %xor0 = xor <8 x i1> %b0, %a

nikic · 2025-01-20T15:46:44Z

llvm/lib/Transforms/Scalar/Reassociate.cpp

  // short-circuited form for code gen, and the source order may have been
  // optimized for the most likely conditions.
-  if (I->getType()->isIntegerTy(1))
+  if (I->getType()->isIntOrIntVectorTy(1))


With the extension to vector types, this comment needs an update. For vector types there's not going to be any short-circuiting.

nikic

LGTM

RKSimon added 2 commits January 15, 2025 12:46

[Reassociate] Disable reassociation for vXi1 types as well as i1 types

450c178

Investigation for llvm#64840

Merge branch 'upstream' into perf/reassociate-bool-vec

286238b

RKSimon requested review from SahilPatidar, dtcxzyw and nikic January 17, 2025 12:12

llvmbot added the llvm:transforms label Jan 17, 2025

nikic reviewed Jan 20, 2025

View reviewed changes

nikic approved these changes Jan 20, 2025

View reviewed changes

RKSimon added 2 commits January 20, 2025 16:20

Merge branch 'upstream' into perf/reassociate-bool-vec

47468ab

Update re-association comment for vXi1 cases.

c2a955c

nikic approved these changes Jan 20, 2025

View reviewed changes

RKSimon added 2 commits January 21, 2025 09:42

Merge branch 'upstream' into perf/reassociate-bool-vec

b050ec8

Fix typo in comment

b9d35c1

RKSimon merged commit b6b18f1 into llvm:main Jan 21, 2025
4 checks passed

RKSimon deleted the perf/reassociate-bool-vec branch January 21, 2025 09:53

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[Reassociate] Don't reassociate vXi1 logical expressions#123329

[Reassociate] Don't reassociate vXi1 logical expressions#123329
RKSimon merged 6 commits intollvm:mainfrom
RKSimon:perf/reassociate-bool-vec

RKSimon commented Jan 17, 2025

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llvmbot commented Jan 17, 2025

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nikic Jan 20, 2025

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RKSimon commented Jan 17, 2025

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llvmbot commented Jan 17, 2025

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nikic Jan 20, 2025

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