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Implement the dot4add_i8packed HLSL Function #99220
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HLSLHLSL Language SupportHLSL Language Supportbackend:DirectXbackend:SPIR-Vbot:HLSLclang:codegenIR generation bugs: mangling, exceptions, etc.IR generation bugs: mangling, exceptions, etc.metaissueIssue to collect references to a group of similar or related issues.Issue to collect references to a group of similar or related issues.
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HLSLHLSL Language SupportHLSL Language Supportbackend:DirectXbackend:SPIR-Vbot:HLSLclang:codegenIR generation bugs: mangling, exceptions, etc.IR generation bugs: mangling, exceptions, etc.metaissueIssue to collect references to a group of similar or related issues.Issue to collect references to a group of similar or related issues.
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dot4add_i8packedclang builtin,dot4add_i8packedclang builtin withhlsl_intrinsics.hdot4add_i8packedtoCheckHLSLBuiltinFunctionCallinSemaChecking.cppdot4add_i8packedtoEmitHLSLBuiltinExprinCGBuiltin.cppclang/test/CodeGenHLSL/builtins/dot4add_i8packed.hlslclang/test/SemaHLSL/BuiltIns/dot4add_i8packed-errors.hlslint_dx_dot4add_i8packedintrinsic inIntrinsicsDirectX.tdDXILOpMappingofint_dx_dot4add_i8packedto163inDXIL.tddot4add_i8packed.llanddot4add_i8packed_errors.lltests inllvm/test/CodeGen/DirectX/int_spv_dot4add_i8packedintrinsic inIntrinsicsSPIRV.tddot4add_i8packedlowering and map it toint_spv_dot4add_i8packedinSPIRVInstructionSelector::selectIntrinsic.llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_i8packed.llDirectX
SPIR-V
OpSDot:
Description:
Signed integer dot product of Vector 1 and Vector 2.
Result Type must be an integer type whose Width must be greater than
or equal to that of the components of Vector 1 and Vector 2.
Vector 1 and Vector 2 must have the same type.
Vector 1 and Vector 2 must be either 32-bit integers (enabled by the
DotProductInput4x8BitPacked capability) or vectors of
integer type (enabled by the DotProductInput4x8Bit or
DotProductInputAll capability).
When Vector 1 and Vector 2 are scalar integer types, Packed Vector
Format must be specified to select how the integers are to be
interpreted as vectors.
All components of the input vectors are sign-extended to the bit width
of the result’s type. The sign-extended input vectors are then
multiplied component-wise and all components of the vector resulting
from the component-wise multiplication are added together. The resulting
value will equal the low-order N bits of the correct result R, where N
is the result width and R is computed with enough precision to avoid
overflow and underflow.
Capability:
DotProduct
Missing before version 1.6.
5 + variable
4450
<id>
Result Type
Result <id>
<id>
Vector 1
<id>
Vector 2
Optional
Packed Vector Format
Packed Vector Format
Test Case(s)
Example 1
HLSL:
Syntax
int dot4add_i8packed(uint a, uint b, int c);Type Description
Minimum Shader Model
This function is supported in the following shader models.
Shader Stages
See also