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Remove the mblaze backend from llvm.
Approval in here http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-July/064169.html llvm-svn: 187145
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129 files changed

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‎llvm/CMakeLists.txt‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -79,7 +79,6 @@ set(LLVM_ALL_TARGETS
7979
CppBackend
8080
Hexagon
8181
Mips
82-
MBlaze
8382
MSP430
8483
NVPTX
8584
PowerPC

‎llvm/autoconf/configure.ac‎

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -407,7 +407,6 @@ AC_CACHE_CHECK([target architecture],[llvm_cv_target_arch],
407407
xcore-*) llvm_cv_target_arch="XCore" ;;
408408
msp430-*) llvm_cv_target_arch="MSP430" ;;
409409
hexagon-*) llvm_cv_target_arch="Hexagon" ;;
410-
mblaze-*) llvm_cv_target_arch="MBlaze" ;;
411410
nvptx-*) llvm_cv_target_arch="NVPTX" ;;
412411
s390x-*) llvm_cv_target_arch="SystemZ" ;;
413412
*) llvm_cv_target_arch="Unknown" ;;
@@ -442,7 +441,6 @@ case $host in
442441
xcore-*) host_arch="XCore" ;;
443442
msp430-*) host_arch="MSP430" ;;
444443
hexagon-*) host_arch="Hexagon" ;;
445-
mblaze-*) host_arch="MBlaze" ;;
446444
s390x-*) host_arch="SystemZ" ;;
447445
*) host_arch="Unknown" ;;
448446
esac
@@ -674,7 +672,6 @@ else
674672
XCore) AC_SUBST(TARGET_HAS_JIT,0) ;;
675673
MSP430) AC_SUBST(TARGET_HAS_JIT,0) ;;
676674
Hexagon) AC_SUBST(TARGET_HAS_JIT,0) ;;
677-
MBlaze) AC_SUBST(TARGET_HAS_JIT,0) ;;
678675
NVPTX) AC_SUBST(TARGET_HAS_JIT,0) ;;
679676
SystemZ) AC_SUBST(TARGET_HAS_JIT,1) ;;
680677
*) AC_SUBST(TARGET_HAS_JIT,0) ;;
@@ -824,7 +821,7 @@ if test "$enableval" = host-only ; then
824821
enableval=host
825822
fi
826823
case "$enableval" in
827-
all) TARGETS_TO_BUILD="X86 Sparc PowerPC AArch64 ARM Mips XCore MSP430 CppBackend MBlaze NVPTX Hexagon SystemZ R600" ;;
824+
all) TARGETS_TO_BUILD="X86 Sparc PowerPC AArch64 ARM Mips XCore MSP430 CppBackend NVPTX Hexagon SystemZ R600" ;;
828825
*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
829826
case "$a_target" in
830827
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -841,7 +838,6 @@ case "$enableval" in
841838
msp430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
842839
cpp) TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
843840
hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
844-
mblaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
845841
nvptx) TARGETS_TO_BUILD="NVPTX $TARGETS_TO_BUILD" ;;
846842
systemz) TARGETS_TO_BUILD="SystemZ $TARGETS_TO_BUILD" ;;
847843
r600) TARGETS_TO_BUILD="R600 $TARGETS_TO_BUILD" ;;
@@ -853,7 +849,6 @@ case "$enableval" in
853849
AArch64) TARGETS_TO_BUILD="AArch64 $TARGETS_TO_BUILD" ;;
854850
ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
855851
Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
856-
MBlaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
857852
XCore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
858853
MSP430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
859854
Hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;

‎llvm/configure‎

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -4033,7 +4033,6 @@ else
40334033
xcore-*) llvm_cv_target_arch="XCore" ;;
40344034
msp430-*) llvm_cv_target_arch="MSP430" ;;
40354035
hexagon-*) llvm_cv_target_arch="Hexagon" ;;
4036-
mblaze-*) llvm_cv_target_arch="MBlaze" ;;
40374036
nvptx-*) llvm_cv_target_arch="NVPTX" ;;
40384037
s390x-*) llvm_cv_target_arch="SystemZ" ;;
40394038
*) llvm_cv_target_arch="Unknown" ;;
@@ -4068,7 +4067,6 @@ case $host in
40684067
xcore-*) host_arch="XCore" ;;
40694068
msp430-*) host_arch="MSP430" ;;
40704069
hexagon-*) host_arch="Hexagon" ;;
4071-
mblaze-*) host_arch="MBlaze" ;;
40724070
s390x-*) host_arch="SystemZ" ;;
40734071
*) host_arch="Unknown" ;;
40744072
esac
@@ -5424,8 +5422,6 @@ else
54245422
MSP430) TARGET_HAS_JIT=0
54255423
;;
54265424
Hexagon) TARGET_HAS_JIT=0
5427-
;;
5428-
MBlaze) TARGET_HAS_JIT=0
54295425
;;
54305426
NVPTX) TARGET_HAS_JIT=0
54315427
;;
@@ -5664,7 +5660,7 @@ if test "$enableval" = host-only ; then
56645660
enableval=host
56655661
fi
56665662
case "$enableval" in
5667-
all) TARGETS_TO_BUILD="X86 Sparc PowerPC AArch64 ARM Mips XCore MSP430 CppBackend MBlaze NVPTX Hexagon SystemZ R600" ;;
5663+
all) TARGETS_TO_BUILD="X86 Sparc PowerPC AArch64 ARM Mips XCore MSP430 CppBackend NVPTX Hexagon SystemZ R600" ;;
56685664
*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
56695665
case "$a_target" in
56705666
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -5681,7 +5677,6 @@ case "$enableval" in
56815677
msp430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
56825678
cpp) TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
56835679
hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
5684-
mblaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
56855680
nvptx) TARGETS_TO_BUILD="NVPTX $TARGETS_TO_BUILD" ;;
56865681
systemz) TARGETS_TO_BUILD="SystemZ $TARGETS_TO_BUILD" ;;
56875682
r600) TARGETS_TO_BUILD="R600 $TARGETS_TO_BUILD" ;;
@@ -5693,7 +5688,6 @@ case "$enableval" in
56935688
AArch64) TARGETS_TO_BUILD="AArch64 $TARGETS_TO_BUILD" ;;
56945689
ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
56955690
Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
5696-
MBlaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
56975691
XCore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
56985692
MSP430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
56995693
Hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
@@ -10551,7 +10545,7 @@ else
1055110545
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
1055210546
lt_status=$lt_dlunknown
1055310547
cat > conftest.$ac_ext <<EOF
10554-
#line 10554 "configure"
10548+
#line 10548 "configure"
1055510549
#include "confdefs.h"
1055610550

1055710551
#if HAVE_DLFCN_H

‎llvm/docs/CodeGenerator.rst‎

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1788,7 +1788,6 @@ Here is the table:
17881788
:raw-html:`<th>Feature</th>`
17891789
:raw-html:`<th>ARM</th>`
17901790
:raw-html:`<th>Hexagon</th>`
1791-
:raw-html:`<th>MBlaze</th>`
17921791
:raw-html:`<th>MSP430</th>`
17931792
:raw-html:`<th>Mips</th>`
17941793
:raw-html:`<th>NVPTX</th>`
@@ -1803,7 +1802,6 @@ Here is the table:
18031802
:raw-html:`<td><a href="#feat_reliable">is generally reliable</a></td>`
18041803
:raw-html:`<td class="yes"></td> <!-- ARM -->`
18051804
:raw-html:`<td class="yes"></td> <!-- Hexagon -->`
1806-
:raw-html:`<td class="no"></td> <!-- MBlaze -->`
18071805
:raw-html:`<td class="unknown"></td> <!-- MSP430 -->`
18081806
:raw-html:`<td class="yes"></td> <!-- Mips -->`
18091807
:raw-html:`<td class="yes"></td> <!-- NVPTX -->`
@@ -1818,7 +1816,6 @@ Here is the table:
18181816
:raw-html:`<td><a href="#feat_asmparser">assembly parser</a></td>`
18191817
:raw-html:`<td class="no"></td> <!-- ARM -->`
18201818
:raw-html:`<td class="no"></td> <!-- Hexagon -->`
1821-
:raw-html:`<td class="yes"></td> <!-- MBlaze -->`
18221819
:raw-html:`<td class="no"></td> <!-- MSP430 -->`
18231820
:raw-html:`<td class="no"></td> <!-- Mips -->`
18241821
:raw-html:`<td class="no"></td> <!-- NVPTX -->`
@@ -1833,7 +1830,6 @@ Here is the table:
18331830
:raw-html:`<td><a href="#feat_disassembler">disassembler</a></td>`
18341831
:raw-html:`<td class="yes"></td> <!-- ARM -->`
18351832
:raw-html:`<td class="no"></td> <!-- Hexagon -->`
1836-
:raw-html:`<td class="yes"></td> <!-- MBlaze -->`
18371833
:raw-html:`<td class="no"></td> <!-- MSP430 -->`
18381834
:raw-html:`<td class="no"></td> <!-- Mips -->`
18391835
:raw-html:`<td class="na"></td> <!-- NVPTX -->`
@@ -1848,7 +1844,6 @@ Here is the table:
18481844
:raw-html:`<td><a href="#feat_inlineasm">inline asm</a></td>`
18491845
:raw-html:`<td class="yes"></td> <!-- ARM -->`
18501846
:raw-html:`<td class="yes"></td> <!-- Hexagon -->`
1851-
:raw-html:`<td class="yes"></td> <!-- MBlaze -->`
18521847
:raw-html:`<td class="unknown"></td> <!-- MSP430 -->`
18531848
:raw-html:`<td class="no"></td> <!-- Mips -->`
18541849
:raw-html:`<td class="yes"></td> <!-- NVPTX -->`
@@ -1863,7 +1858,6 @@ Here is the table:
18631858
:raw-html:`<td><a href="#feat_jit">jit</a></td>`
18641859
:raw-html:`<td class="partial"><a href="#feat_jit_arm">*</a></td> <!-- ARM -->`
18651860
:raw-html:`<td class="no"></td> <!-- Hexagon -->`
1866-
:raw-html:`<td class="no"></td> <!-- MBlaze -->`
18671861
:raw-html:`<td class="unknown"></td> <!-- MSP430 -->`
18681862
:raw-html:`<td class="yes"></td> <!-- Mips -->`
18691863
:raw-html:`<td class="na"></td> <!-- NVPTX -->`
@@ -1878,7 +1872,6 @@ Here is the table:
18781872
:raw-html:`<td><a href="#feat_objectwrite">.o&nbsp;file writing</a></td>`
18791873
:raw-html:`<td class="no"></td> <!-- ARM -->`
18801874
:raw-html:`<td class="no"></td> <!-- Hexagon -->`
1881-
:raw-html:`<td class="yes"></td> <!-- MBlaze -->`
18821875
:raw-html:`<td class="no"></td> <!-- MSP430 -->`
18831876
:raw-html:`<td class="no"></td> <!-- Mips -->`
18841877
:raw-html:`<td class="na"></td> <!-- NVPTX -->`
@@ -1893,7 +1886,6 @@ Here is the table:
18931886
:raw-html:`<td><a hr:raw-html:`ef="#feat_tailcall">tail calls</a></td>`
18941887
:raw-html:`<td class="yes"></td> <!-- ARM -->`
18951888
:raw-html:`<td class="yes"></td> <!-- Hexagon -->`
1896-
:raw-html:`<td class="no"></td> <!-- MBlaze -->`
18971889
:raw-html:`<td class="unknown"></td> <!-- MSP430 -->`
18981890
:raw-html:`<td class="no"></td> <!-- Mips -->`
18991891
:raw-html:`<td class="no"></td> <!-- NVPTX -->`
@@ -1908,7 +1900,6 @@ Here is the table:
19081900
:raw-html:`<td><a href="#feat_segstacks">segmented stacks</a></td>`
19091901
:raw-html:`<td class="no"></td> <!-- ARM -->`
19101902
:raw-html:`<td class="no"></td> <!-- Hexagon -->`
1911-
:raw-html:`<td class="no"></td> <!-- MBlaze -->`
19121903
:raw-html:`<td class="no"></td> <!-- MSP430 -->`
19131904
:raw-html:`<td class="no"></td> <!-- Mips -->`
19141905
:raw-html:`<td class="no"></td> <!-- NVPTX -->`

‎llvm/docs/GettingStarted.rst‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -758,7 +758,7 @@ The following options can be used to set or enable LLVM specific options:
758758
target names that you want available in llc. The target names use all lower
759759
case. The current set of targets is:
760760

761-
``arm, cpp, hexagon, mblaze, mips, mipsel, msp430, powerpc, ptx, sparc, spu,
761+
``arm, cpp, hexagon, mips, mipsel, msp430, powerpc, ptx, sparc, spu,
762762
systemz, x86, x86_64, xcore``.
763763

764764
``--enable-doxygen``

‎llvm/include/llvm/ADT/Triple.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,6 @@ class Triple {
6464
x86, // X86: i[3-9]86
6565
x86_64, // X86-64: amd64, x86_64
6666
xcore, // XCore: xcore
67-
mblaze, // MBlaze: mblaze
6867
nvptx, // NVPTX: 32-bit
6968
nvptx64, // NVPTX: 64-bit
7069
le32, // le32: generic little-endian 32-bit CPU (PNaCl / Emscripten)

‎llvm/include/llvm/IR/CallingConv.h‎

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -93,13 +93,6 @@ namespace CallingConv {
9393
/// Passes all arguments in register or parameter space.
9494
PTX_Device = 72,
9595

96-
/// MBLAZE_INTR - Calling convention used for MBlaze interrupt routines.
97-
MBLAZE_INTR = 73,
98-
99-
/// MBLAZE_INTR - Calling convention used for MBlaze interrupt support
100-
/// routines (i.e. GCC's save_volatiles attribute).
101-
MBLAZE_SVOL = 74,
102-
10396
/// SPIR_FUNC - Calling convention for SPIR non-kernel device functions.
10497
/// No lowering or expansion of arguments.
10598
/// Structures are passed as a pointer to a struct with the byval attribute.

‎llvm/include/llvm/Support/ELF.h‎

Lines changed: 1 addition & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -276,7 +276,6 @@ enum {
276276
EM_STM8 = 186, // STMicroeletronics STM8 8-bit microcontroller
277277
EM_TILE64 = 187, // Tilera TILE64 multicore architecture family
278278
EM_TILEPRO = 188, // Tilera TILEPro multicore architecture family
279-
EM_MICROBLAZE = 189, // Xilinx MicroBlaze 32-bit RISC soft processor core
280279
EM_CUDA = 190, // NVIDIA CUDA architecture
281280
EM_TILEGX = 191, // Tilera TILE-Gx multicore architecture family
282281
EM_CLOUDSHIELD = 192, // CloudShield architecture family
@@ -287,8 +286,7 @@ enum {
287286
EM_RL78 = 197, // Renesas RL78 family
288287
EM_VIDEOCORE5 = 198, // Broadcom VideoCore V processor
289288
EM_78KOR = 199, // Renesas 78KOR family
290-
EM_56800EX = 200, // Freescale 56800EX Digital Signal Controller (DSC)
291-
EM_MBLAZE = 47787 // Xilinx MicroBlaze
289+
EM_56800EX = 200 // Freescale 56800EX Digital Signal Controller (DSC)
292290
};
293291

294292
// Object file classes.
@@ -418,32 +416,6 @@ enum {
418416
R_386_NUM = 43
419417
};
420418

421-
// MBlaze relocations.
422-
enum {
423-
R_MICROBLAZE_NONE = 0,
424-
R_MICROBLAZE_32 = 1,
425-
R_MICROBLAZE_32_PCREL = 2,
426-
R_MICROBLAZE_64_PCREL = 3,
427-
R_MICROBLAZE_32_PCREL_LO = 4,
428-
R_MICROBLAZE_64 = 5,
429-
R_MICROBLAZE_32_LO = 6,
430-
R_MICROBLAZE_SRO32 = 7,
431-
R_MICROBLAZE_SRW32 = 8,
432-
R_MICROBLAZE_64_NONE = 9,
433-
R_MICROBLAZE_32_SYM_OP_SYM = 10,
434-
R_MICROBLAZE_GNU_VTINHERIT = 11,
435-
R_MICROBLAZE_GNU_VTENTRY = 12,
436-
R_MICROBLAZE_GOTPC_64 = 13,
437-
R_MICROBLAZE_GOT_64 = 14,
438-
R_MICROBLAZE_PLT_64 = 15,
439-
R_MICROBLAZE_REL = 16,
440-
R_MICROBLAZE_JUMP_SLOT = 17,
441-
R_MICROBLAZE_GLOB_DAT = 18,
442-
R_MICROBLAZE_GOTOFF_64 = 19,
443-
R_MICROBLAZE_GOTOFF_32 = 20,
444-
R_MICROBLAZE_COPY = 21
445-
};
446-
447419
// ELF Relocation types for PPC32
448420
enum {
449421
R_PPC_NONE = 0, /* No relocation. */

‎llvm/lib/Object/ELFYAML.cpp‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -176,7 +176,6 @@ ScalarEnumerationTraits<ELFYAML::ELF_EM>::enumeration(IO &IO,
176176
ECase(EM_STM8)
177177
ECase(EM_TILE64)
178178
ECase(EM_TILEPRO)
179-
ECase(EM_MICROBLAZE)
180179
ECase(EM_CUDA)
181180
ECase(EM_TILEGX)
182181
ECase(EM_CLOUDSHIELD)
@@ -188,7 +187,6 @@ ScalarEnumerationTraits<ELFYAML::ELF_EM>::enumeration(IO &IO,
188187
ECase(EM_VIDEOCORE5)
189188
ECase(EM_78KOR)
190189
ECase(EM_56800EX)
191-
ECase(EM_MBLAZE)
192190
#undef ECase
193191
}
194192

‎llvm/lib/Support/Triple.cpp‎

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,6 @@ const char *Triple::getArchTypeName(ArchType Kind) {
3838
case x86: return "i386";
3939
case x86_64: return "x86_64";
4040
case xcore: return "xcore";
41-
case mblaze: return "mblaze";
4241
case nvptx: return "nvptx";
4342
case nvptx64: return "nvptx64";
4443
case le32: return "le32";
@@ -63,8 +62,6 @@ const char *Triple::getArchTypePrefix(ArchType Kind) {
6362
case ppc64:
6463
case ppc: return "ppc";
6564

66-
case mblaze: return "mblaze";
67-
6865
case mips:
6966
case mipsel:
7067
case mips64:
@@ -171,7 +168,6 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
171168
.Case("ppc64", ppc64)
172169
.Case("ppc32", ppc)
173170
.Case("ppc", ppc)
174-
.Case("mblaze", mblaze)
175171
.Case("r600", r600)
176172
.Case("hexagon", hexagon)
177173
.Case("sparc", sparc)
@@ -201,7 +197,6 @@ const char *Triple::getArchNameForAssembler() {
201197
.Case("x86_64", "x86_64")
202198
.Case("powerpc", "ppc")
203199
.Case("powerpc64", "ppc64")
204-
.Cases("mblaze", "microblaze", "mblaze")
205200
.Case("arm", "arm")
206201
.Cases("armv4t", "thumbv4t", "armv4t")
207202
.Cases("armv5", "armv5e", "thumbv5", "thumbv5e", "armv5")
@@ -225,7 +220,6 @@ static Triple::ArchType parseArch(StringRef ArchName) {
225220
.Cases("amd64", "x86_64", Triple::x86_64)
226221
.Case("powerpc", Triple::ppc)
227222
.Cases("powerpc64", "ppu", Triple::ppc64)
228-
.Case("mblaze", Triple::mblaze)
229223
.Case("aarch64", Triple::aarch64)
230224
.Cases("arm", "xscale", Triple::arm)
231225
// FIXME: It would be good to replace these with explicit names for all the
@@ -678,7 +672,6 @@ static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
678672
case llvm::Triple::arm:
679673
case llvm::Triple::hexagon:
680674
case llvm::Triple::le32:
681-
case llvm::Triple::mblaze:
682675
case llvm::Triple::mips:
683676
case llvm::Triple::mipsel:
684677
case llvm::Triple::nvptx:
@@ -733,7 +726,6 @@ Triple Triple::get32BitArchVariant() const {
733726
case Triple::arm:
734727
case Triple::hexagon:
735728
case Triple::le32:
736-
case Triple::mblaze:
737729
case Triple::mips:
738730
case Triple::mipsel:
739731
case Triple::nvptx:
@@ -766,7 +758,6 @@ Triple Triple::get64BitArchVariant() const {
766758
case Triple::arm:
767759
case Triple::hexagon:
768760
case Triple::le32:
769-
case Triple::mblaze:
770761
case Triple::msp430:
771762
case Triple::r600:
772763
case Triple::tce:

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