Problem / Background

Apple M5 Pro/Max introduced a new 3-tier CPU architecture: Super + Performance (no Efficiency cores in Pro/Max). The current code only handles the legacy 2-tier P-core/E-core model, causing significant issues on M5 Max where only 6 out of 18 cores are monitored.

1. IOReport channel naming changed (CRITICAL)

On M5 Max, IOReport uses completely new channel prefixes:

Current code at src/device/macos_native/ioreport.rs:794-799 only matches E*/ECPU and P*/PCPU:

• MCPU0x (6 Super cores) → starts with "M" → completely ignored
• MCPU1x (6 Performance cores) → starts with "M" → completely ignored
• PCPUx (6 Performance cores) → starts with "P" → collected as p_cluster (only 6 of 12 Performance cores)
• ECPU → does not exist → e_cluster is empty

Result: Only 6 out of 18 cores are being monitored.

2. sysctl perflevel mapping is wrong

src/device/cpu_macos.rs:362-374 assumes perflevel0 = P-core, perflevel1 = E-core. But on M5 Max:

hw.perflevel0.name: Super
hw.perflevel1.name: Performance
hw.nperflevels: 2

The code hardcodes the assumption without reading hw.perflevelN.name. This causes Super cores to be labeled as "P-CPU" and Performance cores to be labeled as "E-CPU".

3. CoreType enum lacks Super variant

src/device/types.rs:110-115 only has Performance, Efficiency, Standard. No Super variant exists.

4. TUI display only shows P-CPU/E-CPU

src/ui/renderers/cpu_renderer.rs hardcodes "P-CPU" and "E-CPU" labels. M5 Pro/Max needs "S-CPU" and "P-CPU" labels.

5. AppleSiliconCpuInfo struct lacks Super core fields

src/device/types.rs:136-148 only has p_core_* and e_core_* fields.

Proposed Solution

1. Add Super variant to CoreType enum in src/device/types.rs
2. Read hw.perflevelN.name from sysctl to dynamically determine core type names instead of hardcoding perflevel0=P, perflevel1=E
3. Update IOReport channel matching in src/device/macos_native/ioreport.rs to handle MCPU prefix channels, mapping them correctly based on cluster index (MCPU0 = Super, MCPU1 = Performance cluster)
4. Add s_core_count, s_core_utilization, s_cluster_frequency_mhz fields to AppleSiliconCpuInfo
5. Update TUI rendering in src/ui/renderers/cpu_renderer.rs to display "S-CPU" / "P-CPU" for M5, and "P-CPU" / "E-CPU" for M1-M4
6. Handle 3 physical clusters mapping to 2 perflevels (MCPU1 + PCPU are both Performance tier)

Acceptance Criteria

• CoreType::Super variant added and used throughout the codebase
• IOReport correctly parses MCPU0* channels as Super cores and MCPU1* channels as Performance cores
• All 18 cores on M5 Max are monitored (6 Super + 12 Performance)
• sysctl hw.perflevelN.name is read dynamically to determine core type labels
• AppleSiliconCpuInfo includes Super core fields (s_core_count, s_core_utilization, s_cluster_frequency_mhz)
• TUI displays "S-CPU" / "P-CPU" on M5 Pro/Max and "P-CPU" / "E-CPU" on M1-M4
• Backward compatibility with M1/M2/M3/M4 chips is preserved
• No regressions on existing 2-tier P/E architecture

Technical Considerations

• 3 physical IOReport clusters (MCPU0, MCPU1, PCPU) map to 2 sysctl perflevels (Super, Performance). MCPU1 and PCPU are both Performance tier and should be aggregated.
• The MCPU prefix is new to M5; older chips do not use it. Channel matching must be additive, not breaking.
• M5 Pro may have fewer cores per cluster but follows the same naming convention.

Affected Files

• src/device/types.rs — CoreType enum, AppleSiliconCpuInfo struct
• src/device/macos_native/ioreport.rs — IOReport channel parsing
• src/device/cpu_macos.rs — sysctl core count detection
• src/ui/renderers/cpu_renderer.rs — TUI display labels
• src/device/macos_native/metrics.rs — metrics data aggregation

Environment

• Confirmed on: MacBook Pro with Apple M5 Max (Mac17,7)
• 18 cores: 6 Super + 12 Performance
• macOS with hw.perflevel0.name: Super, hw.perflevel1.name: Performance