A systemVerilog implementation of the Game Boy on DE1-SoC
This was for CSEE 4840 Embedded System Design @ Columbia University
To make target files for DE1-SoC
make qsys && make quartus && make rbf
Test
mooneye-gb
BGB
Gambatte
Higan
MESS
VerilogBoy
Ours
cpu instrs
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dmg sound
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instr timing
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interrupt time
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mem timing
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mem timing 2
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oam bug
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Mooneye GB acceptance tests
Test
mooneye-gb
BGB
Gambatte
Higan
MESS
VerilogBoy
Ours
add sp e timing
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call timing
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call timing2
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call cc_timing
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call cc_timing2
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di timing GS
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div timing
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ei sequence
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ei timing
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halt ime0 ei
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halt ime0 nointr_timing
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halt ime1 timing
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halt ime1 timing2 GS
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if ie registers
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intr timing
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jp timing
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jp cc timing
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ld hl sp e timing
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oam dma_restart
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oam dma start
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oam dma timing
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pop timing
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push timing
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rapid di ei
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ret timing
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ret cc timing
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reti timing
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reti intr timing
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rst timing
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Test
mooneye-gb
BGB
Gambatte
Higan
MESS
VerilogBoy
Ours
daa
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Test
mooneye-gb
BGB
Gambatte
Higan
MESS
VerilogBoy
Ours
ie push
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Test
mooneye-gb
BGB
Gambatte
Higan
MESS
VerilogBoy
Ours
basic
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reg_read
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sources dmgABCmgbS
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Test
mooneye-gb
BGB
Gambatte
Higan
MESS
VerilogBoy
Ours
boot sclk align dmgABCmgb
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Test
mooneye-gb
BGB
Gambatte
Higan
MESS
VerilogBoy
Ours
hblank ly scx timing GS
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intr 1 2 timing GS
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intr 2 0 timing
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intr 2 mode0 timing
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intr 2 mode3 timing
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intr 2 oam ok timing
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intr 2 mode0 timing sprites
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lcdon timing dmgABCmgbS
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lcdon write timing GS
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stat irq blocking
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stat lyc onoff
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vblank stat intr GS
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Test
mooneye-gb
BGB
Gambatte
Higan
MESS
VerilogBoy
Ours
div write
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rapid toggle
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tim00 div trigger
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tim00
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tim01 div trigger
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tim01
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tim10 div trigger
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tim10
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tim11 div trigger
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tim11
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tima reload
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tima write reloading
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tma write reloading
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Test
mooneye-gb
BGB
Gambatte
Higan
MESS
VerilogBoy
Ours
MBC1
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MBC5
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Note: MBC3 test ROM was not created at the time of testing.