[SYCL] Add code examples for all SYCL FPGA loop attributes#2764
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bader merged 6 commits intointel:syclfrom Nov 16, 2020
Merged
[SYCL] Add code examples for all SYCL FPGA loop attributes#2764bader merged 6 commits intointel:syclfrom
bader merged 6 commits intointel:syclfrom
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Signed-off-by: Soumi Manna <soumi.manna@intel.com>
This is a followup in intel#2715 (comment). This patch improves the documentation by adding code examples for all FPGA loop attributes that we did not have before. Signed-off-by: Soumi Manna <soumi.manna@intel.com>
… into UpdateDocForLoopAttr
Signed-off-by: Soumi Manna <soumi.manna@intel.com>
MrSidims
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Nov 12, 2020
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May be it would be valuable to also add an example like this:
template<int N>
void bar() {
[[intel::loop_attr(N)]] for(;;) { }
}
Signed-off-by: Soumi Manna <soumi.manna@intel.com>
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@MrSidims Thanks for looking into this. Yes, i agree with you that it would be valuable to add template examples. I have updated doc with the template exmaples. |
MrSidims
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Nov 12, 2020
Signed-off-by: Soumi Manna <soumi.manna@intel.com>
MrSidims
approved these changes
Nov 16, 2020
Fznamznon
approved these changes
Nov 16, 2020
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This is a follow-up in #2715 (comment)
This patch improves the documentation by adding code examples for all FPGA loop
attributes that we did not have before.
Signed-off-by: Soumi Manna soumi.manna@intel.com