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This repository was archived by the owner on Jan 7, 2023. It is now read-only.

Commit 7e181af

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fhvwyYang Rong
fhvwy
authored and
Yang Rong
committed
Enable Coffee Lake support
Little change is needed here because the graphics core is the same as Kaby Lake. Includes all PCI IDs currently supported by the kernel driver in the drm-intel tree (Coffee Lake S, H and U devices in GT 1, 2 and 3 configurations). Signed-off-by: Mark Thompson <sw@jkqxz.net>
1 parent 20c7581 commit 7e181af

3 files changed

Lines changed: 153 additions & 3 deletions

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‎backend/src/backend/gen_program.cpp‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -209,6 +209,8 @@ namespace gbe {
209209
ctx = GBE_NEW(BxtContext, unit, name, deviceID, relaxMath);
210210
} else if (IS_KABYLAKE(deviceID)) {
211211
ctx = GBE_NEW(KblContext, unit, name, deviceID, relaxMath);
212+
} else if (IS_COFFEELAKE(deviceID)) {
213+
ctx = GBE_NEW(KblContext, unit, name, deviceID, relaxMath);
212214
} else if (IS_GEMINILAKE(deviceID)) {
213215
ctx = GBE_NEW(GlkContext, unit, name, deviceID, relaxMath);
214216
}
@@ -328,6 +330,7 @@ namespace gbe {
328330
(IS_SKYLAKE(deviceID) && MATCH_SKL_HEADER(binary)) || \
329331
(IS_BROXTON(deviceID) && MATCH_BXT_HEADER(binary)) || \
330332
(IS_KABYLAKE(deviceID) && MATCH_KBL_HEADER(binary)) || \
333+
(IS_COFFEELAKE(deviceID) && MATCH_KBL_HEADER(binary)) || \
331334
(IS_GEMINILAKE(deviceID) && MATCH_GLK_HEADER(binary)) \
332335
)
333336

@@ -436,6 +439,8 @@ namespace gbe {
436439
FILL_BXT_HEADER(*binary);
437440
}else if(IS_KABYLAKE(prog->deviceID)){
438441
FILL_KBL_HEADER(*binary);
442+
}else if(IS_COFFEELAKE(prog->deviceID)){
443+
FILL_KBL_HEADER(*binary);
439444
}else if(IS_GEMINILAKE(prog->deviceID)){
440445
FILL_GLK_HEADER(*binary);
441446
}else {

‎src/cl_device_data.h‎

Lines changed: 53 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -372,7 +372,59 @@
372372
(devid == PCI_CHIP_GLK_3x6 || \
373373
devid == PCI_CHIP_GLK_2x6)
374374

375-
#define IS_GEN9(devid) (IS_SKYLAKE(devid) || IS_BROXTON(devid) || IS_KABYLAKE(devid) || IS_GEMINILAKE(devid))
375+
#define PCI_CHIP_COFFEELAKE_S_GT1_1 0x3E90
376+
#define PCI_CHIP_COFFEELAKE_S_GT1_2 0x3E93
377+
#define PCI_CHIP_COFFEELAKE_S_GT1_3 0x3E99
378+
379+
#define PCI_CHIP_COFFEELAKE_U_GT1_1 0x3EA1
380+
#define PCI_CHIP_COFFEELAKE_U_GT1_2 0x3EA4
381+
382+
#define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91
383+
#define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92
384+
#define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96
385+
#define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E9A
386+
387+
#define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E94
388+
#define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E9B
389+
390+
#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA0
391+
#define PCI_CHIP_COFFEELAKE_U_GT2_2 0x3EA3
392+
#define PCI_CHIP_COFFEELAKE_U_GT2_3 0x3EA9
393+
394+
#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA2
395+
#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA5
396+
#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA6
397+
#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7
398+
#define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8
399+
400+
#define IS_CFL_GT1(devid) \
401+
(devid == PCI_CHIP_COFFEELAKE_S_GT1_1 || \
402+
devid == PCI_CHIP_COFFEELAKE_S_GT1_2 || \
403+
devid == PCI_CHIP_COFFEELAKE_S_GT1_3 || \
404+
devid == PCI_CHIP_COFFEELAKE_U_GT1_1 || \
405+
devid == PCI_CHIP_COFFEELAKE_U_GT1_2)
406+
407+
#define IS_CFL_GT2(devid) \
408+
(devid == PCI_CHIP_COFFEELAKE_S_GT2_1 || \
409+
devid == PCI_CHIP_COFFEELAKE_S_GT2_2 || \
410+
devid == PCI_CHIP_COFFEELAKE_S_GT2_3 || \
411+
devid == PCI_CHIP_COFFEELAKE_S_GT2_4 || \
412+
devid == PCI_CHIP_COFFEELAKE_H_GT2_1 || \
413+
devid == PCI_CHIP_COFFEELAKE_H_GT2_2 || \
414+
devid == PCI_CHIP_COFFEELAKE_U_GT2_1 || \
415+
devid == PCI_CHIP_COFFEELAKE_U_GT2_2 || \
416+
devid == PCI_CHIP_COFFEELAKE_U_GT2_3)
417+
418+
#define IS_CFL_GT3(devid) \
419+
(devid == PCI_CHIP_COFFEELAKE_U_GT3_1 || \
420+
devid == PCI_CHIP_COFFEELAKE_U_GT3_2 || \
421+
devid == PCI_CHIP_COFFEELAKE_U_GT3_3 || \
422+
devid == PCI_CHIP_COFFEELAKE_U_GT3_4 || \
423+
devid == PCI_CHIP_COFFEELAKE_U_GT3_5)
424+
425+
#define IS_COFFEELAKE(devid) (IS_CFL_GT1(devid) || IS_CFL_GT2(devid) || IS_CFL_GT3(devid))
426+
427+
#define IS_GEN9(devid) (IS_SKYLAKE(devid) || IS_BROXTON(devid) || IS_KABYLAKE(devid) || IS_GEMINILAKE(devid) || IS_COFFEELAKE(devid))
376428

377429
#define MAX_OCLVERSION(devid) (IS_GEN9(devid) ? 200 : 120)
378430

‎src/cl_device_id.c‎

Lines changed: 95 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -274,6 +274,36 @@ static struct _cl_device_id intel_glk12eu_device = {
274274
#include "cl_gen9_device.h"
275275
};
276276

277+
static struct _cl_device_id intel_cfl_gt1_device = {
278+
.max_compute_unit = 12,
279+
.max_thread_per_unit = 7,
280+
.sub_slice_count = 2,
281+
.max_work_item_sizes = {512, 512, 512},
282+
.max_work_group_size = 256,
283+
.max_clock_frequency = 1000,
284+
#include "cl_gen9_device.h"
285+
};
286+
287+
static struct _cl_device_id intel_cfl_gt2_device = {
288+
.max_compute_unit = 24,
289+
.max_thread_per_unit = 7,
290+
.sub_slice_count = 3,
291+
.max_work_item_sizes = {512, 512, 512},
292+
.max_work_group_size = 256,
293+
.max_clock_frequency = 1000,
294+
#include "cl_gen9_device.h"
295+
};
296+
297+
static struct _cl_device_id intel_cfl_gt3_device = {
298+
.max_compute_unit = 48,
299+
.max_thread_per_unit = 7,
300+
.sub_slice_count = 6,
301+
.max_work_item_sizes = {512, 512, 512},
302+
.max_work_group_size = 256,
303+
.max_clock_frequency = 1000,
304+
#include "cl_gen9_device.h"
305+
};
306+
277307
LOCAL cl_device_id
278308
cl_get_gt_device(cl_device_type device_type)
279309
{
@@ -785,6 +815,64 @@ cl_get_gt_device(cl_device_type device_type)
785815
cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
786816
break;
787817

818+
case PCI_CHIP_COFFEELAKE_S_GT1_1:
819+
case PCI_CHIP_COFFEELAKE_S_GT1_2:
820+
case PCI_CHIP_COFFEELAKE_S_GT1_3:
821+
DECL_INFO_STRING(cfl_gt1_break, intel_cfl_gt1_device, name, "Intel(R) UHD Graphics Coffee Lake Desktop GT1");
822+
case PCI_CHIP_COFFEELAKE_U_GT1_1:
823+
case PCI_CHIP_COFFEELAKE_U_GT1_2:
824+
DECL_INFO_STRING(cfl_gt1_break, intel_cfl_gt1_device, name, "Intel(R) UHD Graphics Coffee Lake Mobile GT1");
825+
cfl_gt1_break:
826+
intel_cfl_gt1_device.device_id = device_id;
827+
intel_cfl_gt1_device.platform = cl_get_platform_default();
828+
ret = &intel_cfl_gt1_device;
829+
cl_intel_platform_get_default_extension(ret);
830+
#ifdef ENABLE_FP64
831+
cl_intel_platform_enable_extension(ret, cl_khr_fp64_ext_id);
832+
#endif
833+
cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
834+
break;
835+
836+
case PCI_CHIP_COFFEELAKE_S_GT2_1:
837+
case PCI_CHIP_COFFEELAKE_S_GT2_2:
838+
case PCI_CHIP_COFFEELAKE_S_GT2_3:
839+
case PCI_CHIP_COFFEELAKE_S_GT2_4:
840+
DECL_INFO_STRING(cfl_gt2_break, intel_cfl_gt2_device, name, "Intel(R) UHD Graphics Coffee Lake Desktop GT2");
841+
case PCI_CHIP_COFFEELAKE_H_GT2_1:
842+
case PCI_CHIP_COFFEELAKE_H_GT2_2:
843+
DECL_INFO_STRING(cfl_gt2_break, intel_cfl_gt2_device, name, "Intel(R) UHD Graphics Coffee Lake Halo GT2");
844+
case PCI_CHIP_COFFEELAKE_U_GT2_1:
845+
case PCI_CHIP_COFFEELAKE_U_GT2_2:
846+
case PCI_CHIP_COFFEELAKE_U_GT2_3:
847+
DECL_INFO_STRING(cfl_gt2_break, intel_cfl_gt2_device, name, "Intel(R) UHD Graphics Coffee Lake Mobile GT2");
848+
cfl_gt2_break:
849+
intel_cfl_gt2_device.device_id = device_id;
850+
intel_cfl_gt2_device.platform = cl_get_platform_default();
851+
ret = &intel_cfl_gt2_device;
852+
cl_intel_platform_get_default_extension(ret);
853+
#ifdef ENABLE_FP64
854+
cl_intel_platform_enable_extension(ret, cl_khr_fp64_ext_id);
855+
#endif
856+
cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
857+
break;
858+
859+
case PCI_CHIP_COFFEELAKE_U_GT3_1:
860+
case PCI_CHIP_COFFEELAKE_U_GT3_2:
861+
case PCI_CHIP_COFFEELAKE_U_GT3_3:
862+
case PCI_CHIP_COFFEELAKE_U_GT3_4:
863+
case PCI_CHIP_COFFEELAKE_U_GT3_5:
864+
DECL_INFO_STRING(cfl_gt3_break, intel_cfl_gt3_device, name, "Intel(R) UHD Graphics Coffee Lake Mobile GT3");
865+
cfl_gt3_break:
866+
intel_cfl_gt3_device.device_id = device_id;
867+
intel_cfl_gt3_device.platform = cl_get_platform_default();
868+
ret = &intel_cfl_gt3_device;
869+
cl_intel_platform_get_default_extension(ret);
870+
#ifdef ENABLE_FP64
871+
cl_intel_platform_enable_extension(ret, cl_khr_fp64_ext_id);
872+
#endif
873+
cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
874+
break;
875+
788876
case PCI_CHIP_SANDYBRIDGE_BRIDGE:
789877
case PCI_CHIP_SANDYBRIDGE_GT1:
790878
case PCI_CHIP_SANDYBRIDGE_GT2:
@@ -992,7 +1080,10 @@ LOCAL cl_bool is_gen_device(cl_device_id device) {
9921080
device == &intel_kbl_gt3_device ||
9931081
device == &intel_kbl_gt4_device ||
9941082
device == &intel_glk18eu_device ||
995-
device == &intel_glk12eu_device;
1083+
device == &intel_glk12eu_device ||
1084+
device == &intel_cfl_gt1_device ||
1085+
device == &intel_cfl_gt2_device ||
1086+
device == &intel_cfl_gt3_device;
9961087
}
9971088

9981089
LOCAL cl_int
@@ -1420,7 +1511,9 @@ cl_device_get_version(cl_device_id device, cl_int *ver)
14201511
|| device == &intel_bxt18eu_device || device == &intel_bxt12eu_device || device == &intel_kbl_gt1_device
14211512
|| device == &intel_kbl_gt2_device || device == &intel_kbl_gt3_device
14221513
|| device == &intel_kbl_gt4_device || device == &intel_kbl_gt15_device
1423-
|| device == &intel_glk18eu_device || device == &intel_glk12eu_device) {
1514+
|| device == &intel_glk18eu_device || device == &intel_glk12eu_device
1515+
|| device == &intel_cfl_gt1_device || device == &intel_cfl_gt1_device
1516+
|| device == &intel_cfl_gt3_device) {
14241517
*ver = 9;
14251518
} else
14261519
return CL_INVALID_VALUE;

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