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@HiFiPhile HiFiPhile commented Oct 5, 2025

Describe the PR
FIFO allocation needs additional space for EP disable status, which is 1 location for each EP.
MPSiz needs to be set correctly for EP0 in order to reserve Rx FIFO correctly.

Also fix preset with espressif, who needs Ninja single config.

Copilot AI review requested due to automatic review settings October 5, 2025 16:41
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Pull Request Overview

This PR fixes USB enumeration issues with the DWC2 USB controller when EP0 max packet size is 8 bytes by ensuring the RX FIFO size is at least 64 words. Additionally, it updates the CMake preset generation to handle Espressif boards with Ninja single config generator.

  • Fixed DWC2 RX FIFO allocation to use minimum 64 words regardless of EP0 size
  • Corrected EP0 max packet size handling during bus reset to use configured size
  • Updated preset generation to separate Espressif boards with single-config Ninja generator

Reviewed Changes

Copilot reviewed 3 out of 3 changed files in this pull request and generated 1 comment.

File Description
src/portable/synopsys/dwc2/dcd_dwc2.c Fixed RX FIFO sizing and EP0 packet size handling for proper enumeration
tools/gen_presets.py Added logic to generate separate presets for Espressif boards with Ninja generator
hw/bsp/BoardPresets.json Reorganized board presets to use single config for Espressif boards

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hathach commented Oct 6, 2025

@codex review

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Codex Review: Didn't find any major issues. You're on a roll.

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TU_ATTR_ALWAYS_INLINE static inline uint16_t calc_device_grxfsiz(uint16_t largest_ep_size, uint8_t ep_count) {
return 13 + 1 + 2 * ((largest_ep_size / 4) + 1) + 2 * ep_count;
return 13 + 1 + 2 * ((largest_ep_size / 4) + 1) + 1 * (2 * ep_count) + 2 * ep_count;
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@hathach hathach Oct 6, 2025

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is it correct that we need 1*2*ep_count, grx is for EPOUT only ? Does EP in disabled status also take a byte from grxfifo as well ?

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I think the manual means every endpoint:

❑ An additional location for EPDisable status for each endpoint is also required.

And we also need to add another field:

❑ Along with last packet of each endpoint, transfer complete status information is also pushed in to the FIFO.

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programming guide 2.1.3 method 2 to calculate shared rx
image

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Hum the manual is unclear, it says in Dedicated TxFIFO mode RxFIFO is the same as Shared TxFIFO mode. Then transfer complete status and EPDisable status mentioned in 2.1.1.1 are not in 2.1.3.1 formula...

I'm going to do some tests of minimal buffer size required.

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@HiFiPhile HiFiPhile Oct 6, 2025

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When I retest I found it is still broken with a hub.

With that hub 1st Get Descriptor Device length is 18 bytes, and enumeration is broken by #1102

USBD Setup Received 80 06 00 01 00 00 12 00
  Get Descriptor Device
  Queue EP 80 with 8 bytes ...
USBD Xfer Complete on EP 80 with 8 bytes
  Queue EP 80 with 8 bytes ...

In my test USB 3 CV set wLength to 8 for 1st request, may we change #1102 to use 8 bytes length ? @kasjer

image

Current formula is correct in fact, the real issue is MPS of EP0 needs to be set accordingly, without setting MPS to 8 more FIFO size will be needed.

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@HiFiPhile let me retest with USB 3 CV tool, it was failing with Dialog (now Renesas) device DA1469x.

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Sorry I must mixed up the capture data, in device selection phase it uses wLength=8, but with actual test wLength is indeed 18.

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Good news, there is no need to change usbd.c, my hub will try to use wLength=64 after initial wlength=18 attempt. Previous failure is fact caused by something else in dwc2 driver.

USBD Bus Reset : Full Speed
USBD Suspend  Skipped

USBD Setup Received 80 06 00 01 00 00 12 00
  Get Descriptor Device
  Queue EP 80 with 8 bytes ...
USBD Xfer Complete on EP 80 with 8 bytes
  Queue EP 80 with 8 bytes ...

USBD Setup Received 80 06 00 01 00 00 12 00
  Get Descriptor Device
  Queue EP 80 with 8 bytes ...
USBD Xfer Complete on EP 80 with 8 bytes
  Queue EP 80 with 8 bytes ...
USBD Xfer Complete on EP 80 with 8 bytes
  Queue EP 80 with 2 bytes ...
USBD Xfer Complete on EP 80 with 2 bytes
  Queue EP 00 with 0 bytes ...
USBD Xfer Complete on EP 00 with 0 bytes
USBD Bus Reset : Full Speed
USBD Suspend  Skipped

USBD Setup Received 80 06 00 01 00 00 40 00
  Get Descriptor Device
  Queue EP 80 with 8 bytes ...
USBD Xfer Complete on EP 80 with 8 bytes
  Queue EP 00 with 0 bytes ...
USBD Xfer Complete on EP 00 with 0 bytes
USBD Bus Reset : Full Speed

USBD Setup Received 00 05 36 00 00 00 00 00
  Set Address
USBD Xfer Complete on EP 80 with 0 bytes

USBD Setup Received 80 06 00 01 00 00 12 00
  Get Descriptor Device
  Queue EP 80 with 8 bytes ...
USBD Xfer Complete on EP 80 with 8 bytes
  Queue EP 80 with 8 bytes ...
USBD Xfer Complete on EP 80 with 8 bytes
  Queue EP 80 with 2 bytes ...
USBD Xfer Complete on EP 80 with 2 bytes
  Queue EP 00 with 0 bytes ...
USBD Xfer Complete on EP 00 with 0 bytes

Signed-off-by: Mengsk <admin@hifiphile.com>
Signed-off-by: Mengsk <admin@hifiphile.com>
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perfect, thank you

@hathach hathach merged commit 0fab57b into hathach:master Oct 9, 2025
191 of 195 checks passed
@HiFiPhile HiFiPhile deleted the dwc2_ep0 branch November 25, 2025 10:00
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