This is a port of https://github.com/gtaylormb/opl3_fpga with the OPL3 superset removed. It has been tested on a ZYBO board.
+----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+------+-------+------------+-----------+-------+
| Slice LUTs | 749 | 0 | 0 | 17600 | 4.26 |
| LUT as Logic | 631 | 0 | 0 | 17600 | 3.59 |
| LUT as Memory | 118 | 0 | 0 | 6000 | 1.97 |
| LUT as Distributed RAM | 68 | 0 | | | |
| LUT as Shift Register | 50 | 0 | | | |
| Slice Registers | 920 | 0 | 0 | 35200 | 2.61 |
| Register as Flip Flop | 920 | 0 | 0 | 35200 | 2.61 |
| Register as Latch | 0 | 0 | 0 | 35200 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 8800 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 4400 | 0.00 |
+----------------------------+------+-------+------------+-----------+-------+
+------------------------------------------------------+----------------------------------------------------------------+------------+------------+---------+------+-----+--------+--------+------------+
| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks |
+------------------------------------------------------+----------------------------------------------------------------+------------+------------+---------+------+-----+--------+--------+------------+
| design_1_wrapper | (top) | 749 | 631 | 68 | 50 | 920 | 0 | 5 | 1 |
| (design_1_wrapper) | (top) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| design_1_i | design_1 | 749 | 631 | 68 | 50 | 920 | 0 | 5 | 1 |
| mmcm_125 | design_1_mmcm_125_0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| inst | design_1_mmcm_125_0_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| opl3_fpga_0 | design_1_opl3_fpga_0_0 | 535 | 451 | 68 | 16 | 602 | 0 | 5 | 1 |
| (opl3_fpga_0) | design_1_opl3_fpga_0_0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| inst | opl3_fpga_v2_0 | 535 | 451 | 68 | 16 | 602 | 0 | 5 | 1 |
| i2s | i2s | 16 | 16 | 0 | 0 | 40 | 0 | 0 | 0 |
| opl2 | opl2 | 505 | 421 | 68 | 16 | 538 | 0 | 5 | 1 |