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lsun100jwrdegoede
lsun100
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jwrdegoede
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platform/mellanox: Add BlueField-3 support in the tmfifo driver
BlueField-3 uses the same control registers in tmfifo access but at different addresses. This commit replaces the offset reference with pointers, and set up these pointers in the probe functions accordingly. Signed-off-by: Liming Sun <limings@nvidia.com> Reviewed-by: David Thompson <davthompson@nvidia.com> Reviewed-by: Vadim Pasternak <vadimp@nvidia.com> Link: https://lore.kernel.org/r/20221018133303.243920-1-limings@nvidia.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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2 files changed

+74
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‎drivers/platform/mellanox/mlxbf-tmfifo-regs.h‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -60,4 +60,14 @@
6060
#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0)
6161
#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32)
6262

63+
/* BF3 register offsets within resource 0. */
64+
#define MLXBF_TMFIFO_RX_DATA_BF3 0x0000
65+
#define MLXBF_TMFIFO_TX_DATA_BF3 0x1000
66+
67+
/* BF3 register offsets within resource 1. */
68+
#define MLXBF_TMFIFO_RX_STS_BF3 0x0000
69+
#define MLXBF_TMFIFO_RX_CTL_BF3 0x0008
70+
#define MLXBF_TMFIFO_TX_STS_BF3 0x0100
71+
#define MLXBF_TMFIFO_TX_CTL_BF3 0x0108
72+
6373
#endif /* !defined(__MLXBF_TMFIFO_REGS_H__) */

‎drivers/platform/mellanox/mlxbf-tmfifo.c‎

Lines changed: 64 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,9 @@
4747
/* Message with data needs at least two words (for header & data). */
4848
#define MLXBF_TMFIFO_DATA_MIN_WORDS 2
4949

50+
/* ACPI UID for BlueField-3. */
51+
#define TMFIFO_BF3_UID 1
52+
5053
struct mlxbf_tmfifo;
5154

5255
/**
@@ -136,12 +139,26 @@ struct mlxbf_tmfifo_irq_info {
136139
int index;
137140
};
138141

142+
/**
143+
* mlxbf_tmfifo_io - Structure of the TmFifo IO resource (for both rx & tx)
144+
* @ctl: control register offset (TMFIFO_RX_CTL / TMFIFO_TX_CTL)
145+
* @sts: status register offset (TMFIFO_RX_STS / TMFIFO_TX_STS)
146+
* @data: data register offset (TMFIFO_RX_DATA / TMFIFO_TX_DATA)
147+
*/
148+
struct mlxbf_tmfifo_io {
149+
void __iomem *ctl;
150+
void __iomem *sts;
151+
void __iomem *data;
152+
};
153+
139154
/**
140155
* mlxbf_tmfifo - Structure of the TmFifo
141156
* @vdev: array of the virtual devices running over the TmFifo
142157
* @lock: lock to protect the TmFifo access
143-
* @rx_base: mapped register base address for the Rx FIFO
144-
* @tx_base: mapped register base address for the Tx FIFO
158+
* @res0: mapped resource block 0
159+
* @res1: mapped resource block 1
160+
* @rx: rx io resource
161+
* @tx: tx io resource
145162
* @rx_fifo_size: number of entries of the Rx FIFO
146163
* @tx_fifo_size: number of entries of the Tx FIFO
147164
* @pend_events: pending bits for deferred events
@@ -155,8 +172,10 @@ struct mlxbf_tmfifo_irq_info {
155172
struct mlxbf_tmfifo {
156173
struct mlxbf_tmfifo_vdev *vdev[MLXBF_TMFIFO_VDEV_MAX];
157174
struct mutex lock; /* TmFifo lock */
158-
void __iomem *rx_base;
159-
void __iomem *tx_base;
175+
void __iomem *res0;
176+
void __iomem *res1;
177+
struct mlxbf_tmfifo_io rx;
178+
struct mlxbf_tmfifo_io tx;
160179
int rx_fifo_size;
161180
int tx_fifo_size;
162181
unsigned long pend_events;
@@ -472,7 +491,7 @@ static int mlxbf_tmfifo_get_rx_avail(struct mlxbf_tmfifo *fifo)
472491
{
473492
u64 sts;
474493

475-
sts = readq(fifo->rx_base + MLXBF_TMFIFO_RX_STS);
494+
sts = readq(fifo->rx.sts);
476495
return FIELD_GET(MLXBF_TMFIFO_RX_STS__COUNT_MASK, sts);
477496
}
478497

@@ -489,7 +508,7 @@ static int mlxbf_tmfifo_get_tx_avail(struct mlxbf_tmfifo *fifo, int vdev_id)
489508
else
490509
tx_reserve = 1;
491510

492-
sts = readq(fifo->tx_base + MLXBF_TMFIFO_TX_STS);
511+
sts = readq(fifo->tx.sts);
493512
count = FIELD_GET(MLXBF_TMFIFO_TX_STS__COUNT_MASK, sts);
494513
return fifo->tx_fifo_size - tx_reserve - count;
495514
}
@@ -525,7 +544,7 @@ static void mlxbf_tmfifo_console_tx(struct mlxbf_tmfifo *fifo, int avail)
525544
/* Write header. */
526545
hdr.type = VIRTIO_ID_CONSOLE;
527546
hdr.len = htons(size);
528-
writeq(*(u64 *)&hdr, fifo->tx_base + MLXBF_TMFIFO_TX_DATA);
547+
writeq(*(u64 *)&hdr, fifo->tx.data);
529548

530549
/* Use spin-lock to protect the 'cons->tx_buf'. */
531550
spin_lock_irqsave(&fifo->spin_lock[0], flags);
@@ -542,7 +561,7 @@ static void mlxbf_tmfifo_console_tx(struct mlxbf_tmfifo *fifo, int avail)
542561
memcpy((u8 *)&data + seg, cons->tx_buf.buf,
543562
sizeof(u64) - seg);
544563
}
545-
writeq(data, fifo->tx_base + MLXBF_TMFIFO_TX_DATA);
564+
writeq(data, fifo->tx.data);
546565

547566
if (size >= sizeof(u64)) {
548567
cons->tx_buf.tail = (cons->tx_buf.tail + sizeof(u64)) %
@@ -573,7 +592,7 @@ static void mlxbf_tmfifo_rxtx_word(struct mlxbf_tmfifo_vring *vring,
573592

574593
/* Read a word from FIFO for Rx. */
575594
if (is_rx)
576-
data = readq(fifo->rx_base + MLXBF_TMFIFO_RX_DATA);
595+
data = readq(fifo->rx.data);
577596

578597
if (vring->cur_len + sizeof(u64) <= len) {
579598
/* The whole word. */
@@ -595,7 +614,7 @@ static void mlxbf_tmfifo_rxtx_word(struct mlxbf_tmfifo_vring *vring,
595614

596615
/* Write the word into FIFO for Tx. */
597616
if (!is_rx)
598-
writeq(data, fifo->tx_base + MLXBF_TMFIFO_TX_DATA);
617+
writeq(data, fifo->tx.data);
599618
}
600619

601620
/*
@@ -617,7 +636,7 @@ static void mlxbf_tmfifo_rxtx_header(struct mlxbf_tmfifo_vring *vring,
617636
/* Read/Write packet header. */
618637
if (is_rx) {
619638
/* Drain one word from the FIFO. */
620-
*(u64 *)&hdr = readq(fifo->rx_base + MLXBF_TMFIFO_RX_DATA);
639+
*(u64 *)&hdr = readq(fifo->rx.data);
621640

622641
/* Skip the length 0 packets (keepalive). */
623642
if (hdr.len == 0)
@@ -661,7 +680,7 @@ static void mlxbf_tmfifo_rxtx_header(struct mlxbf_tmfifo_vring *vring,
661680
hdr.type = (vring->vdev_id == VIRTIO_ID_NET) ?
662681
VIRTIO_ID_NET : VIRTIO_ID_CONSOLE;
663682
hdr.len = htons(vring->pkt_len - hdr_len);
664-
writeq(*(u64 *)&hdr, fifo->tx_base + MLXBF_TMFIFO_TX_DATA);
683+
writeq(*(u64 *)&hdr, fifo->tx.data);
665684
}
666685

667686
vring->cur_len = hdr_len;
@@ -1157,7 +1176,7 @@ static void mlxbf_tmfifo_set_threshold(struct mlxbf_tmfifo *fifo)
11571176
u64 ctl;
11581177

11591178
/* Get Tx FIFO size and set the low/high watermark. */
1160-
ctl = readq(fifo->tx_base + MLXBF_TMFIFO_TX_CTL);
1179+
ctl = readq(fifo->tx.ctl);
11611180
fifo->tx_fifo_size =
11621181
FIELD_GET(MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK, ctl);
11631182
ctl = (ctl & ~MLXBF_TMFIFO_TX_CTL__LWM_MASK) |
@@ -1166,17 +1185,17 @@ static void mlxbf_tmfifo_set_threshold(struct mlxbf_tmfifo *fifo)
11661185
ctl = (ctl & ~MLXBF_TMFIFO_TX_CTL__HWM_MASK) |
11671186
FIELD_PREP(MLXBF_TMFIFO_TX_CTL__HWM_MASK,
11681187
fifo->tx_fifo_size - 1);
1169-
writeq(ctl, fifo->tx_base + MLXBF_TMFIFO_TX_CTL);
1188+
writeq(ctl, fifo->tx.ctl);
11701189

11711190
/* Get Rx FIFO size and set the low/high watermark. */
1172-
ctl = readq(fifo->rx_base + MLXBF_TMFIFO_RX_CTL);
1191+
ctl = readq(fifo->rx.ctl);
11731192
fifo->rx_fifo_size =
11741193
FIELD_GET(MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_MASK, ctl);
11751194
ctl = (ctl & ~MLXBF_TMFIFO_RX_CTL__LWM_MASK) |
11761195
FIELD_PREP(MLXBF_TMFIFO_RX_CTL__LWM_MASK, 0);
11771196
ctl = (ctl & ~MLXBF_TMFIFO_RX_CTL__HWM_MASK) |
11781197
FIELD_PREP(MLXBF_TMFIFO_RX_CTL__HWM_MASK, 1);
1179-
writeq(ctl, fifo->rx_base + MLXBF_TMFIFO_RX_CTL);
1198+
writeq(ctl, fifo->rx.ctl);
11801199
}
11811200

11821201
static void mlxbf_tmfifo_cleanup(struct mlxbf_tmfifo *fifo)
@@ -1197,8 +1216,15 @@ static int mlxbf_tmfifo_probe(struct platform_device *pdev)
11971216
struct virtio_net_config net_config;
11981217
struct device *dev = &pdev->dev;
11991218
struct mlxbf_tmfifo *fifo;
1219+
u64 dev_id;
12001220
int i, rc;
12011221

1222+
rc = acpi_dev_uid_to_integer(ACPI_COMPANION(dev), &dev_id);
1223+
if (rc) {
1224+
dev_err(dev, "Cannot retrieve UID\n");
1225+
return rc;
1226+
}
1227+
12021228
fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);
12031229
if (!fifo)
12041230
return -ENOMEM;
@@ -1209,14 +1235,30 @@ static int mlxbf_tmfifo_probe(struct platform_device *pdev)
12091235
mutex_init(&fifo->lock);
12101236

12111237
/* Get the resource of the Rx FIFO. */
1212-
fifo->rx_base = devm_platform_ioremap_resource(pdev, 0);
1213-
if (IS_ERR(fifo->rx_base))
1214-
return PTR_ERR(fifo->rx_base);
1238+
fifo->res0 = devm_platform_ioremap_resource(pdev, 0);
1239+
if (IS_ERR(fifo->res0))
1240+
return PTR_ERR(fifo->res0);
12151241

12161242
/* Get the resource of the Tx FIFO. */
1217-
fifo->tx_base = devm_platform_ioremap_resource(pdev, 1);
1218-
if (IS_ERR(fifo->tx_base))
1219-
return PTR_ERR(fifo->tx_base);
1243+
fifo->res1 = devm_platform_ioremap_resource(pdev, 1);
1244+
if (IS_ERR(fifo->res1))
1245+
return PTR_ERR(fifo->res1);
1246+
1247+
if (dev_id == TMFIFO_BF3_UID) {
1248+
fifo->rx.ctl = fifo->res1 + MLXBF_TMFIFO_RX_CTL_BF3;
1249+
fifo->rx.sts = fifo->res1 + MLXBF_TMFIFO_RX_STS_BF3;
1250+
fifo->rx.data = fifo->res0 + MLXBF_TMFIFO_RX_DATA_BF3;
1251+
fifo->tx.ctl = fifo->res1 + MLXBF_TMFIFO_TX_CTL_BF3;
1252+
fifo->tx.sts = fifo->res1 + MLXBF_TMFIFO_TX_STS_BF3;
1253+
fifo->tx.data = fifo->res0 + MLXBF_TMFIFO_TX_DATA_BF3;
1254+
} else {
1255+
fifo->rx.ctl = fifo->res0 + MLXBF_TMFIFO_RX_CTL;
1256+
fifo->rx.sts = fifo->res0 + MLXBF_TMFIFO_RX_STS;
1257+
fifo->rx.data = fifo->res0 + MLXBF_TMFIFO_RX_DATA;
1258+
fifo->tx.ctl = fifo->res1 + MLXBF_TMFIFO_TX_CTL;
1259+
fifo->tx.sts = fifo->res1 + MLXBF_TMFIFO_TX_STS;
1260+
fifo->tx.data = fifo->res1 + MLXBF_TMFIFO_TX_DATA;
1261+
}
12201262

12211263
platform_set_drvdata(pdev, fifo);
12221264

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