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vadimp-nvidiajwrdegoede
vadimp-nvidia
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jwrdegoede
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platform/x86: mlx-platform: Extend FAN and LED configuration to support new MQM97xx systems
Add support for new system types "MQM97xx", which is based on Mellanox Quantum-2 ASIC. It provides up to 64x400GB/s (IB) full bidirectional bandwidth per port using PAM-4 modulation. The system support 32 OSFP cages that can provide 64x400GB/s per port (two ports/cage). The system fits standard 1U racks. System is equipped with seven fan drawers and with per fan drawer LED on backport panel and uses two-bytes for exposing CPLD Part Number versions. System is recognized by "DMI_BOARD_NAME" match, when this field is set to "VMOD0010". Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Oleksandr Shamray <oleksandrs@nvidia.com> Link: https://lore.kernel.org/r/20211023094022.4193813-2-vadimp@nvidia.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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‎drivers/platform/x86/mlx-platform.c‎

Lines changed: 55 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,9 +27,13 @@
2727
#define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02
2828
#define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET 0x03
2929
#define MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET 0x04
30+
#define MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET 0x05
3031
#define MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET 0x06
32+
#define MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET 0x07
3133
#define MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET 0x08
34+
#define MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET 0x09
3235
#define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET 0x0a
36+
#define MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET 0x0b
3337
#define MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET 0x1c
3438
#define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d
3539
#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e
@@ -127,6 +131,8 @@
127131
#define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee
128132
#define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef
129133
#define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0
134+
#define MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET 0xf1
135+
#define MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET 0xf2
130136
#define MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET 0xf3
131137
#define MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET 0xf4
132138
#define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0xf5
@@ -194,7 +200,7 @@
194200
#define MLXPLAT_CPLD_PWR_EXT_MASK GENMASK(3, 0)
195201
#define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0)
196202
#define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0)
197-
#define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(5, 0)
203+
#define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(6, 0)
198204
#define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4)
199205
#define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0)
200206
#define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4)
@@ -933,6 +939,14 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_fan_items_data[] = {
933939
.bit = BIT(5),
934940
.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
935941
},
942+
{
943+
.label = "fan7",
944+
.reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
945+
.mask = BIT(6),
946+
.capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
947+
.bit = BIT(6),
948+
.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
949+
},
936950
};
937951

938952
static struct mlxreg_core_item mlxplat_mlxcpld_default_ng_items[] = {
@@ -2164,6 +2178,20 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = {
21642178
.capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
21652179
.bit = BIT(5),
21662180
},
2181+
{
2182+
.label = "fan7:green",
2183+
.reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,
2184+
.mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2185+
.capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2186+
.bit = BIT(6),
2187+
},
2188+
{
2189+
.label = "fan7:orange",
2190+
.reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,
2191+
.mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2192+
.capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2193+
.bit = BIT(6),
2194+
},
21672195
{
21682196
.label = "uid:blue",
21692197
.reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
@@ -3526,6 +3554,20 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = {
35263554
.bit = BIT(3),
35273555
.reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
35283556
},
3557+
{
3558+
.label = "tacho13",
3559+
.reg = MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET,
3560+
.mask = GENMASK(7, 0),
3561+
.capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
3562+
.bit = BIT(4),
3563+
},
3564+
{
3565+
.label = "tacho14",
3566+
.reg = MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET,
3567+
.mask = GENMASK(7, 0),
3568+
.capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
3569+
.bit = BIT(5),
3570+
},
35293571
{
35303572
.label = "conf",
35313573
.capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET,
@@ -3835,9 +3877,13 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
38353877
case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
38363878
case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
38373879
case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:
3880+
case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET:
38383881
case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:
3882+
case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET:
38393883
case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET:
3884+
case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET:
38403885
case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET:
3886+
case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET:
38413887
case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET:
38423888
case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
38433889
case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
@@ -3935,6 +3981,8 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
39353981
case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET:
39363982
case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
39373983
case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
3984+
case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET:
3985+
case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET:
39383986
case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
39393987
case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
39403988
case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
@@ -3958,9 +4006,13 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
39584006
case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
39594007
case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
39604008
case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:
4009+
case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET:
39614010
case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:
4011+
case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET:
39624012
case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET:
4013+
case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET:
39634014
case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET:
4015+
case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET:
39644016
case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET:
39654017
case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
39664018
case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
@@ -4050,6 +4102,8 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
40504102
case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET:
40514103
case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
40524104
case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
4105+
case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET:
4106+
case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET:
40534107
case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
40544108
case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
40554109
case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:

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