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vadimp-nvidiajwrdegoede
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platform/x86: mlx-platform: Introduce support for COMe NVSwitch management module for Vulcan chassis
The Vulcan is chassis containing Nvidia's Hopper dGPU (GH100), NVswitch (LS10) based HGX baseboard and COMe NVSwitch management module. The system is built for artificial intelligence and accelerated analytics applications. Vulcan is offered as an HGX product to cloud service providers and OEMs, who intend to build fully interconnected GPU systems for large scale deployments. Driver is extended to support new COMe NVSwitch management module. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Oleksandr Shamray <oleksandrs@nvidia.com> Link: https://lore.kernel.org/r/20220711084559.62447-5-vadimp@nvidia.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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‎drivers/platform/x86/mlx-platform.c‎

Lines changed: 269 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,9 @@
6767
#define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0x43
6868
#define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0x44
6969
#define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0x45
70+
#define MLXPLAT_CPLD_LPC_REG_GWP_OFFSET 0x4a
71+
#define MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET 0x4b
72+
#define MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET 0x4c
7073
#define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50
7174
#define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51
7275
#define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52
@@ -209,6 +212,7 @@
209212
#define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4)
210213
#define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0)
211214
#define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4)
215+
#define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0)
212216
#define MLXPLAT_CPLD_I2C_CAP_BIT 0x04
213217
#define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5, MLXPLAT_CPLD_I2C_CAP_BIT)
214218

@@ -2027,6 +2031,38 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_modular_data = {
20272031
.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
20282032
};
20292033

2034+
/* Platform hotplug for NVLink blade systems family data */
2035+
static struct mlxreg_core_data mlxplat_mlxcpld_global_wp_items_data[] = {
2036+
{
2037+
.label = "global_wp_grant",
2038+
.reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET,
2039+
.mask = MLXPLAT_CPLD_GWP_MASK,
2040+
.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
2041+
},
2042+
};
2043+
2044+
static struct mlxreg_core_item mlxplat_mlxcpld_nvlink_blade_items[] = {
2045+
{
2046+
.data = mlxplat_mlxcpld_global_wp_items_data,
2047+
.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2048+
.reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET,
2049+
.mask = MLXPLAT_CPLD_GWP_MASK,
2050+
.count = ARRAY_SIZE(mlxplat_mlxcpld_global_wp_items_data),
2051+
.inversed = 0,
2052+
.health = false,
2053+
},
2054+
};
2055+
2056+
static
2057+
struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_nvlink_blade_data = {
2058+
.items = mlxplat_mlxcpld_nvlink_blade_items,
2059+
.counter = ARRAY_SIZE(mlxplat_mlxcpld_nvlink_blade_items),
2060+
.cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
2061+
.mask = MLXPLAT_CPLD_AGGR_MASK_COMEX,
2062+
.cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
2063+
.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
2064+
};
2065+
20302066
/* Platform led default data */
20312067
static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = {
20322068
{
@@ -3589,6 +3625,203 @@ static struct mlxreg_core_platform_data mlxplat_modular_regs_io_data = {
35893625
.counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_regs_io_data),
35903626
};
35913627

3628+
/* Platform register access for NVLink blade systems family data */
3629+
static struct mlxreg_core_data mlxplat_mlxcpld_nvlink_blade_regs_io_data[] = {
3630+
{
3631+
.label = "cpld1_version",
3632+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
3633+
.bit = GENMASK(7, 0),
3634+
.mode = 0444,
3635+
},
3636+
{
3637+
.label = "cpld1_pn",
3638+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
3639+
.bit = GENMASK(15, 0),
3640+
.mode = 0444,
3641+
.regnum = 2,
3642+
},
3643+
{
3644+
.label = "cpld1_version_min",
3645+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
3646+
.bit = GENMASK(7, 0),
3647+
.mode = 0444,
3648+
},
3649+
{
3650+
.label = "reset_aux_pwr_or_ref",
3651+
.reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3652+
.mask = GENMASK(7, 0) & ~BIT(2),
3653+
.mode = 0444,
3654+
},
3655+
{
3656+
.label = "reset_from_comex",
3657+
.reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3658+
.mask = GENMASK(7, 0) & ~BIT(4),
3659+
.mode = 0444,
3660+
},
3661+
{
3662+
.label = "reset_comex_pwr_fail",
3663+
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3664+
.mask = GENMASK(7, 0) & ~BIT(3),
3665+
.mode = 0444,
3666+
},
3667+
{
3668+
.label = "reset_platform",
3669+
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3670+
.mask = GENMASK(7, 0) & ~BIT(4),
3671+
.mode = 0444,
3672+
},
3673+
{
3674+
.label = "reset_soc",
3675+
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3676+
.mask = GENMASK(7, 0) & ~BIT(5),
3677+
.mode = 0444,
3678+
},
3679+
{
3680+
.label = "reset_comex_wd",
3681+
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3682+
.mask = GENMASK(7, 0) & ~BIT(6),
3683+
.mode = 0444,
3684+
},
3685+
{
3686+
.label = "reset_voltmon_upgrade_fail",
3687+
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3688+
.mask = GENMASK(7, 0) & ~BIT(0),
3689+
.mode = 0444,
3690+
},
3691+
{
3692+
.label = "reset_system",
3693+
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3694+
.mask = GENMASK(7, 0) & ~BIT(1),
3695+
.mode = 0444,
3696+
},
3697+
{
3698+
.label = "reset_sw_pwr_off",
3699+
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3700+
.mask = GENMASK(7, 0) & ~BIT(2),
3701+
.mode = 0444,
3702+
},
3703+
{
3704+
.label = "reset_comex_thermal",
3705+
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3706+
.mask = GENMASK(7, 0) & ~BIT(3),
3707+
.mode = 0444,
3708+
},
3709+
{
3710+
.label = "reset_reload_bios",
3711+
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3712+
.mask = GENMASK(7, 0) & ~BIT(5),
3713+
.mode = 0444,
3714+
},
3715+
{
3716+
.label = "reset_ac_pwr_fail",
3717+
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3718+
.mask = GENMASK(7, 0) & ~BIT(6),
3719+
.mode = 0444,
3720+
},
3721+
{
3722+
.label = "pwr_cycle",
3723+
.reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3724+
.mask = GENMASK(7, 0) & ~BIT(2),
3725+
.mode = 0200,
3726+
},
3727+
{
3728+
.label = "pwr_down",
3729+
.reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3730+
.mask = GENMASK(7, 0) & ~BIT(3),
3731+
.mode = 0200,
3732+
},
3733+
{
3734+
.label = "global_wp_request",
3735+
.reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
3736+
.mask = GENMASK(7, 0) & ~BIT(0),
3737+
.mode = 0644,
3738+
},
3739+
{
3740+
.label = "jtag_enable",
3741+
.reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
3742+
.mask = GENMASK(7, 0) & ~BIT(4),
3743+
.mode = 0644,
3744+
},
3745+
{
3746+
.label = "comm_chnl_ready",
3747+
.reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
3748+
.mask = GENMASK(7, 0) & ~BIT(6),
3749+
.mode = 0200,
3750+
},
3751+
{
3752+
.label = "bios_safe_mode",
3753+
.reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3754+
.mask = GENMASK(7, 0) & ~BIT(4),
3755+
.mode = 0444,
3756+
},
3757+
{
3758+
.label = "bios_active_image",
3759+
.reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3760+
.mask = GENMASK(7, 0) & ~BIT(5),
3761+
.mode = 0444,
3762+
},
3763+
{
3764+
.label = "bios_auth_fail",
3765+
.reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3766+
.mask = GENMASK(7, 0) & ~BIT(6),
3767+
.mode = 0444,
3768+
},
3769+
{
3770+
.label = "bios_upgrade_fail",
3771+
.reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3772+
.mask = GENMASK(7, 0) & ~BIT(7),
3773+
.mode = 0444,
3774+
},
3775+
{
3776+
.label = "voltreg_update_status",
3777+
.reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET,
3778+
.mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK,
3779+
.bit = 5,
3780+
.mode = 0444,
3781+
},
3782+
{
3783+
.label = "vpd_wp",
3784+
.reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
3785+
.mask = GENMASK(7, 0) & ~BIT(3),
3786+
.mode = 0644,
3787+
},
3788+
{
3789+
.label = "pcie_asic_reset_dis",
3790+
.reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
3791+
.mask = GENMASK(7, 0) & ~BIT(4),
3792+
.mode = 0644,
3793+
},
3794+
{
3795+
.label = "global_wp_response",
3796+
.reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET,
3797+
.mask = GENMASK(7, 0) & ~BIT(0),
3798+
.mode = 0444,
3799+
},
3800+
{
3801+
.label = "config1",
3802+
.reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET,
3803+
.bit = GENMASK(7, 0),
3804+
.mode = 0444,
3805+
},
3806+
{
3807+
.label = "config2",
3808+
.reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET,
3809+
.bit = GENMASK(7, 0),
3810+
.mode = 0444,
3811+
},
3812+
{
3813+
.label = "ufm_version",
3814+
.reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET,
3815+
.bit = GENMASK(7, 0),
3816+
.mode = 0444,
3817+
},
3818+
};
3819+
3820+
static struct mlxreg_core_platform_data mlxplat_nvlink_blade_regs_io_data = {
3821+
.data = mlxplat_mlxcpld_nvlink_blade_regs_io_data,
3822+
.counter = ARRAY_SIZE(mlxplat_mlxcpld_nvlink_blade_regs_io_data),
3823+
};
3824+
35923825
/* Platform FAN default */
35933826
static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = {
35943827
{
@@ -3974,6 +4207,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
39744207
case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
39754208
case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET:
39764209
case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:
4210+
case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET:
4211+
case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET:
39774212
case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
39784213
case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
39794214
case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET:
@@ -4067,6 +4302,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
40674302
case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET:
40684303
case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET:
40694304
case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:
4305+
case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET:
4306+
case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET:
4307+
case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET:
40704308
case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
40714309
case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
40724310
case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
@@ -4197,6 +4435,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
41974435
case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET:
41984436
case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET:
41994437
case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:
4438+
case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET:
4439+
case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET:
4440+
case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET:
42004441
case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
42014442
case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
42024443
case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
@@ -4629,6 +4870,28 @@ static int __init mlxplat_dmi_modular_matched(const struct dmi_system_id *dmi)
46294870
return 1;
46304871
}
46314872

4873+
static int __init mlxplat_dmi_nvlink_blade_matched(const struct dmi_system_id *dmi)
4874+
{
4875+
int i;
4876+
4877+
mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
4878+
mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
4879+
mlxplat_mux_data = mlxplat_default_mux_data;
4880+
mlxplat_hotplug = &mlxplat_mlxcpld_nvlink_blade_data;
4881+
mlxplat_hotplug->deferred_nr =
4882+
mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
4883+
for (i = 0; i < mlxplat_mux_num; i++) {
4884+
mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
4885+
mlxplat_mux_data[i].n_values =
4886+
ARRAY_SIZE(mlxplat_msn21xx_channels);
4887+
}
4888+
mlxplat_regs_io = &mlxplat_nvlink_blade_regs_io_data;
4889+
mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
4890+
mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400;
4891+
4892+
return 1;
4893+
}
4894+
46324895
static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
46334896
{
46344897
.callback = mlxplat_dmi_default_wc_matched,
@@ -4691,6 +4954,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
46914954
DMI_MATCH(DMI_BOARD_NAME, "VMOD0011"),
46924955
},
46934956
},
4957+
{
4958+
.callback = mlxplat_dmi_nvlink_blade_matched,
4959+
.matches = {
4960+
DMI_MATCH(DMI_BOARD_NAME, "VMOD0015"),
4961+
},
4962+
},
46944963
{
46954964
.callback = mlxplat_dmi_msn274x_matched,
46964965
.matches = {

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