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vadimp-nvidiajwrdegoede
vadimp-nvidia
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platform/x86: mlx-platform: Add support for new system SGN2410
Add support for new system type, which is a water-cooling flavor of the VMOD001 system class, equipped with 48xSFP28 and 8xQSFP28 100G Ethernet ports. System is recognized by "DMI_BOARD_NAME" and " DMI_PRODUCT_SKU" matches, when these fields are set respectively to "VMOD001" and "HI138". Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Oleksandr Shamray <oleksandrs@nvidia.com> Link: https://lore.kernel.org/r/20211023094022.4193813-4-vadimp@nvidia.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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‎drivers/platform/x86/mlx-platform.c‎

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Original file line numberDiff line numberDiff line change
@@ -533,6 +533,21 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_items_data[] = {
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},
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};
535535

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static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_wc_items_data[] = {
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{
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.label = "pwr1",
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.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
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.mask = BIT(0),
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.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
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},
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{
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.label = "pwr2",
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.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
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.mask = BIT(1),
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.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
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},
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};
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static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = {
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{
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.label = "fan1",
@@ -661,6 +676,46 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_data = {
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.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
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};
663678

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static struct mlxreg_core_item mlxplat_mlxcpld_default_wc_items[] = {
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{
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.data = mlxplat_mlxcpld_comex_psu_items_data,
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.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER,
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.reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
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.mask = MLXPLAT_CPLD_PSU_MASK,
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.count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data),
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.inversed = 1,
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.health = false,
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},
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{
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.data = mlxplat_mlxcpld_default_pwr_wc_items_data,
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.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER,
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.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
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.mask = MLXPLAT_CPLD_PWR_MASK,
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.count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data),
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.inversed = 0,
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.health = false,
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},
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{
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.data = mlxplat_mlxcpld_default_asic_items_data,
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.aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
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.reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
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.mask = MLXPLAT_CPLD_ASIC_MASK,
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.count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
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.inversed = 0,
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.health = true,
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},
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};
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static
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struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_wc_data = {
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.items = mlxplat_mlxcpld_default_wc_items,
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.counter = ARRAY_SIZE(mlxplat_mlxcpld_default_wc_items),
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.cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
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.mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
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.cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
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.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
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};
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static
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struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_comex_data = {
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.items = mlxplat_mlxcpld_comex_items,
@@ -2018,6 +2073,35 @@ static struct mlxreg_core_platform_data mlxplat_default_led_data = {
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.counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_data),
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};
20202075

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/* Platform led default data for water cooling */
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static struct mlxreg_core_data mlxplat_mlxcpld_default_led_wc_data[] = {
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{
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.label = "status:green",
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.reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
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.mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
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},
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{
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.label = "status:red",
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.reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
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.mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
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},
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{
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.label = "psu:green",
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.reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
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.mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
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},
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{
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.label = "psu:red",
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.reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
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.mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
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},
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};
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static struct mlxreg_core_platform_data mlxplat_default_led_wc_data = {
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.data = mlxplat_mlxcpld_default_led_wc_data,
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.counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_wc_data),
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};
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20212105
/* Platform led MSN21xx system family data */
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static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_led_data[] = {
20232107
{
@@ -4311,6 +4395,28 @@ static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi)
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return 1;
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}
43134397

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static int __init mlxplat_dmi_default_wc_matched(const struct dmi_system_id *dmi)
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{
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int i;
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mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
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mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
4404+
mlxplat_mux_data = mlxplat_default_mux_data;
4405+
for (i = 0; i < mlxplat_mux_num; i++) {
4406+
mlxplat_mux_data[i].values = mlxplat_default_channels[i];
4407+
mlxplat_mux_data[i].n_values =
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ARRAY_SIZE(mlxplat_default_channels[i]);
4409+
}
4410+
mlxplat_hotplug = &mlxplat_mlxcpld_default_wc_data;
4411+
mlxplat_hotplug->deferred_nr =
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mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
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mlxplat_led = &mlxplat_default_led_wc_data;
4414+
mlxplat_regs_io = &mlxplat_default_regs_io_data;
4415+
mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
4416+
4417+
return 1;
4418+
}
4419+
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static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi)
43154421
{
43164422
int i;
@@ -4474,6 +4580,13 @@ static int __init mlxplat_dmi_modular_matched(const struct dmi_system_id *dmi)
44744580
}
44754581

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static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
4583+
{
4584+
.callback = mlxplat_dmi_default_wc_matched,
4585+
.matches = {
4586+
DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"),
4587+
DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI138"),
4588+
},
4589+
},
44774590
{
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.callback = mlxplat_dmi_default_matched,
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.matches = {

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