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vadimp-nvidiajwrdegoede
vadimp-nvidia
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jwrdegoede
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platform/x86: mlx-platform: Add support for systems equipped with two ASICs
Motivation is to support new systems equipped with two ASICs. Extend driver with: - The second ASIC health event. - Per ASIC reset control, triggering reset of ASIC internal resources and restarting ASIC initialization flow. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Oleksandr Shamray <oleksandrs@nvidia.com> Link: https://lore.kernel.org/r/20220711084559.62447-4-vadimp@nvidia.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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‎drivers/platform/x86/mlx-platform.c‎

Lines changed: 51 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@
3434
#define MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET 0x09
3535
#define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET 0x0a
3636
#define MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET 0x0b
37+
#define MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET 0x19
3738
#define MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET 0x1c
3839
#define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d
3940
#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e
@@ -69,6 +70,9 @@
6970
#define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50
7071
#define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51
7172
#define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52
73+
#define MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET 0x53
74+
#define MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET 0x54
75+
#define MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET 0x55
7276
#define MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET 0x56
7377
#define MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET 0x57
7478
#define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58
@@ -193,6 +197,7 @@
193197
MLXPLAT_CPLD_AGGR_MASK_LC_ACT | \
194198
MLXPLAT_CPLD_AGGR_MASK_LC_SDWN)
195199
#define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1
200+
#define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2 BIT(2)
196201
#define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6)
197202
#define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0)
198203
#define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0)
@@ -588,6 +593,15 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_asic_items_data[] = {
588593
},
589594
};
590595

596+
static struct mlxreg_core_data mlxplat_mlxcpld_default_asic2_items_data[] = {
597+
{
598+
.label = "asic2",
599+
.reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET,
600+
.mask = MLXPLAT_CPLD_ASIC_MASK,
601+
.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
602+
},
603+
};
604+
591605
static struct mlxreg_core_item mlxplat_mlxcpld_default_items[] = {
592606
{
593607
.data = mlxplat_mlxcpld_default_psu_items_data,
@@ -1151,6 +1165,15 @@ static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = {
11511165
.inversed = 0,
11521166
.health = true,
11531167
},
1168+
{
1169+
.data = mlxplat_mlxcpld_default_asic2_items_data,
1170+
.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1171+
.reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET,
1172+
.mask = MLXPLAT_CPLD_ASIC_MASK,
1173+
.count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic2_items_data),
1174+
.inversed = 0,
1175+
.health = true,
1176+
}
11541177
};
11551178

11561179
static
@@ -1160,7 +1183,7 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = {
11601183
.cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
11611184
.mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX,
11621185
.cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
1163-
.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
1186+
.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2,
11641187
};
11651188

11661189
static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = {
@@ -2856,6 +2879,18 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
28562879
.bit = GENMASK(7, 0),
28572880
.mode = 0444,
28582881
},
2882+
{
2883+
.label = "asic_reset",
2884+
.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET,
2885+
.mask = GENMASK(7, 0) & ~BIT(3),
2886+
.mode = 0200,
2887+
},
2888+
{
2889+
.label = "asic2_reset",
2890+
.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET,
2891+
.mask = GENMASK(7, 0) & ~BIT(2),
2892+
.mode = 0200,
2893+
},
28592894
{
28602895
.label = "reset_long_pb",
28612896
.reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
@@ -2995,6 +3030,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
29953030
.bit = 1,
29963031
.mode = 0444,
29973032
},
3033+
{
3034+
.label = "asic2_health",
3035+
.reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET,
3036+
.mask = MLXPLAT_CPLD_ASIC_MASK,
3037+
.bit = 1,
3038+
.mode = 0444,
3039+
},
29983040
{
29993041
.label = "fan_dir",
30003042
.reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION,
@@ -3934,6 +3976,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
39343976
case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:
39353977
case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
39363978
case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
3979+
case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET:
3980+
case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET:
39373981
case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
39383982
case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
39393983
case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET:
@@ -4026,6 +4070,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
40264070
case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
40274071
case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
40284072
case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
4073+
case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET:
4074+
case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET:
4075+
case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET:
40294076
case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
40304077
case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
40314078
case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
@@ -4153,6 +4200,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
41534200
case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
41544201
case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
41554202
case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
4203+
case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET:
4204+
case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET:
4205+
case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET:
41564206
case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
41574207
case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
41584208
case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:

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