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Pull requests: gem5/gem5

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Pull requests list

stdlib: Use atomic_noncaching switching to atomic CPU with Ruby stdlib The gem5 standard library. Code typically found under "src/pythongem5"
#3061 opened Apr 2, 2026 by abmerop Loading…
1
mem-garnet: complete HeteroGarnet per-vnet dedicated links for XY routing mem-garnet The Garnet subcomponent of Ruby
#3060 opened Apr 2, 2026 by polpetras Loading…
arch-riscv: Add RELEASE flag to all CBO instructions arch-riscv The RISC-V ISA
#3058 opened Apr 2, 2026 by zhongchengyong Loading…
misc: bump mypy from 1.19.1 to 1.20.0 misc Anything outside of the current labeling categories
#3056 opened Apr 2, 2026 by dependabot bot Loading…
@Harshil2107
arch-riscv: raise IllegalInstFault for vlseg/vsseg nf*EMUL>8 arch-riscv The RISC-V ISA
#3055 opened Apr 1, 2026 by polpetras Loading…
arch-riscv: Add KVM support arch-riscv The RISC-V ISA cpu-kvm gem5's KVM CPU
#3053 opened Apr 1, 2026 by selimsandal Loading…
24
arch-x86: add MPK support arch-x86 The X86 ISA
#3051 opened Mar 31, 2026 by Schmitz48 Loading…
misc: Only run VEGA_X86 GPU tests in weeklies for code coverage github gem5 files necessary for GitHub integration. Found in ".github" misc Anything outside of the current labeling categories
#3050 opened Mar 30, 2026 by erin-le Loading…
8
build(deps): bump pygments from 2.17.2 to 2.20.0 in /ext/pybind11/docs dependencies Pull requests that update a dependency file python gem5's Python SimObject wrapping and infrastructure
#3049 opened Mar 30, 2026 by dependabot bot Loading…
@erin-le
arch-riscv: Fix some vslideup instructions arch-riscv The RISC-V ISA
#3048 opened Mar 29, 2026 by EzElephant Loading…
build(deps): bump cryptography from 44.0.1 to 46.0.6 in /util/gem5-resources-manager dependencies Pull requests that update a dependency file python gem5's Python SimObject wrapping and infrastructure
#3045 opened Mar 28, 2026 by dependabot bot Loading…
@erin-le
cpu-o3: fix pinned reg assert on fault-induced squash cpu-o3 gem5's Out-Of-Order CPU
#3040 opened Mar 27, 2026 by polpetras Loading…
1
2
feat(riscv): Added support SV48 in pagetable_walker, SV48 is not supp… arch-riscv The RISC-V ISA
#3032 opened Mar 25, 2026 by NikitaRusanovskii Loading…
RFC: Update to use c++20 misc Anything outside of the current labeling categories
#3028 opened Mar 24, 2026 by ylldummy Loading…
18
arch-x86: x87 FPU movfp/lfpimm micro-ops use wrong dataSize arch-x86 The X86 ISA
#3026 opened Mar 22, 2026 by hakan-demirli Loading…
1
cpu-o3: Release LSQ requests when no access is required cpu-o3 gem5's Out-Of-Order CPU
#3022 opened Mar 20, 2026 by BobbyRBruce Loading…
13
arch-x86: Fix decoding of REX prefixes in invalid positions arch-x86 The X86 ISA
#3021 opened Mar 20, 2026 by jxors Loading…
6
misc: Proof of concept for bazel integration: DO NOT MERGE misc Anything outside of the current labeling categories
#3004 opened Mar 12, 2026 by powerjg • Draft
tests, arch-arm: Update arm fs tests to use obtain_resources arch-arm The ARM ISA tests gem5's Testing Infrastructure
#3003 opened Mar 11, 2026 by Harshil2107 • Draft
2
arch-x86: Revert " implement FSGSBASE" arch-x86 The X86 ISA
#2996 opened Mar 9, 2026 by BobbyRBruce • Draft
sim,python: Document and name the hypercall exit APIs python gem5's Python SimObject wrapping and infrastructure sim General gem5 Simulation Components
#2983 opened Mar 3, 2026 by BobbyRBruce • Draft
6
mem-ruby: add StashOnce*PoC and StashOnce* flow mem-ruby Ruby caches, structures, and protocols
#2975 opened Mar 2, 2026 by tsyw Loading…
5
build: replace SCons with CMake+Ninja and Bazel build systems misc Anything outside of the current labeling categories scons Scons. gem5's Build System
#2969 opened Feb 28, 2026 by SihaoLiu Loading…
21
Implement arm linux syscall 403 clock_gettime arch-arm The ARM ISA
#2960 opened Feb 24, 2026 by dbear496 Loading…
6
configs: implement MI300X PSP partitioning configs gem5's Preprepared Python Configuration scripts. Typically found in "configs" gpu gem5's GPU Simulation infrastructure
#2959 opened Feb 24, 2026 by ronpower7 Loading…
29
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