#ifndef RISCV_CSR_H

#define RISCV_CSR_H

#include <stdint.h>

#if __riscv_xlen==32

typedef uint32_t uint_xlen_t;

typedef uint32_t uint_csr32_t;

typedef uint32_t uint_csr64_t;

#elif __riscv_xlen==64

typedef uint64_t uint_xlen_t;

typedef uint32_t uint_csr32_t;

typedef uint64_t uint_csr64_t;

#error "Unknown XLEN"

#if defined(__riscv_arch_test)

#if !defined(__riscv_zicsr)

#error "-march must include zicsr to access CSRs"

static inline uint_xlen_t csr_read_misa(void) {

uint_xlen_t value;

__asm__ volatile ("csrr %0, misa"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline void csr_write_misa(uint_xlen_t value) {

__asm__ volatile ("csrw misa, %0"

: /* output: none */

: "r" (value) /* input : from register */

: /* clobbers: none */);

}

static inline uint_xlen_t csr_read_write_misa(uint_xlen_t new_value) {

uint_xlen_t prev_value;

__asm__ volatile ("csrrw %0, misa, %1"

: "=r" (prev_value) /* output: register %0 */

: "r" (new_value) /* input : register */

: /* clobbers: none */);

return prev_value;

}

static inline uint32_t csr_read_mvendorid(void) {

uint_csr32_t value;

__asm__ volatile ("csrr %0, mvendorid"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline uint_xlen_t csr_read_marchid(void) {

uint_xlen_t value;

__asm__ volatile ("csrr %0, marchid"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline uint_xlen_t csr_read_mimpid(void) {

uint_xlen_t value;

__asm__ volatile ("csrr %0, mimpid"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline uint_xlen_t csr_read_mhartid(void) {

uint_xlen_t value;

__asm__ volatile ("csrr %0, mhartid"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline uint_xlen_t csr_read_mstatus(void) {

uint_xlen_t value;

__asm__ volatile ("csrr %0, mstatus"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline void csr_write_mstatus(uint_xlen_t value) {

__asm__ volatile ("csrw mstatus, %0"

: /* output: none */

: "r" (value) /* input : from register */

: /* clobbers: none */);

}

static inline uint_xlen_t csr_read_write_mstatus(uint_xlen_t new_value) {

uint_xlen_t prev_value;

__asm__ volatile ("csrrw %0, mstatus, %1"

: "=r" (prev_value) /* output: register %0 */

: "r" (new_value) /* input : register */

: /* clobbers: none */);

return prev_value;

}

static inline void csr_set_bits_mstatus(uint_xlen_t mask) {

__asm__ volatile ("csrrs zero, mstatus, %0"

: /* output: none */

: "r" (mask) /* input : register */

: /* clobbers: none */);

}

static inline void csr_clr_bits_mstatus(uint_xlen_t mask) {

__asm__ volatile ("csrrc zero, mstatus, %0"

: /* output: none */

: "r" (mask) /* input : register */

: /* clobbers: none */);

}

static inline uint_xlen_t csr_read_set_bits_mstatus(uint_xlen_t mask) {

uint_xlen_t value;

__asm__ volatile ("csrrs %0, mstatus, %1"

: "=r" (value) /* output: register %0 */

: "r" (mask) /* input : register */

: /* clobbers: none */);

return value;

}

static inline uint_xlen_t csr_read_clr_bits_mstatus(uint_xlen_t mask) {

uint_xlen_t value;

__asm__ volatile ("csrrc %0, mstatus, %1"

: "=r" (value) /* output: register %0 */

: "r" (mask) /* input : register */

: /* clobbers: none */);

return value;

}

#define CSR_WRITE_IMM_MSTATUS(VALUE) \

__asm__ volatile ("csrrwi zero, mstatus, %0" \

: /* output: none */ \

: "i" (VALUE) /* input : immediate */ \

: /* clobbers: none */)

#define CSR_SET_BITS_IMM_MSTATUS(MASK) \

__asm__ volatile ("csrrsi zero, mstatus, %0" \

: /* output: none */ \

: "i" (MASK) /* input : immediate */ \

: /* clobbers: none */)

#define CSR_CLR_BITS_IMM_MSTATUS(MASK) \

__asm__ volatile ("csrrci zero, mstatus, %0" \

: /* output: none */ \

: "i" (MASK) /* input : immediate */ \

: /* clobbers: none */)

#define MSTATUS_MIE_BIT_OFFSET 3

#define MSTATUS_MIE_BIT_WIDTH 1

#define MSTATUS_MIE_BIT_MASK 0x8

#define MSTATUS_MIE_ALL_SET_MASK 0x1

#define MSTATUS_SIE_BIT_OFFSET 2

#define MSTATUS_SIE_BIT_WIDTH 1

#define MSTATUS_SIE_BIT_MASK 0x4

#define MSTATUS_SIE_ALL_SET_MASK 0x1

#define MSTATUS_MPIE_BIT_OFFSET 7

#define MSTATUS_MPIE_BIT_WIDTH 1

#define MSTATUS_MPIE_BIT_MASK 0x80

#define MSTATUS_MPIE_ALL_SET_MASK 0x1

#define MSTATUS_SPIE_BIT_OFFSET 5

#define MSTATUS_SPIE_BIT_WIDTH 1

#define MSTATUS_SPIE_BIT_MASK 0x20

#define MSTATUS_SPIE_ALL_SET_MASK 0x1

#define MSTATUS_MPRV_BIT_OFFSET 17

#define MSTATUS_MPRV_BIT_WIDTH 1

#define MSTATUS_MPRV_BIT_MASK 0x20000

#define MSTATUS_MPRV_ALL_SET_MASK 0x1

#define MSTATUS_MPP_BIT_OFFSET 11

#define MSTATUS_MPP_BIT_WIDTH 2

#define MSTATUS_MPP_BIT_MASK 0x1800

#define MSTATUS_MPP_ALL_SET_MASK 0x3

#define MSTATUS_SPP_BIT_OFFSET 8

#define MSTATUS_SPP_BIT_WIDTH 1

#define MSTATUS_SPP_BIT_MASK 0x100

#define MSTATUS_SPP_ALL_SET_MASK 0x1

static inline uint_xlen_t csr_read_mstatush(void) {

uint_xlen_t value;

__asm__ volatile ("csrr %0, mstatush"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline void csr_write_mstatush(uint_xlen_t value) {

__asm__ volatile ("csrw mstatush, %0"

: /* output: none */

: "r" (value) /* input : from register */

: /* clobbers: none */);

}

static inline uint_xlen_t csr_read_write_mstatush(uint_xlen_t new_value) {

uint_xlen_t prev_value;

__asm__ volatile ("csrrw %0, mstatush, %1"

: "=r" (prev_value) /* output: register %0 */

: "r" (new_value) /* input : register */

: /* clobbers: none */);

return prev_value;

}

static inline uint_xlen_t csr_read_mtvec(void) {

uint_xlen_t value;

__asm__ volatile ("csrr %0, mtvec"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline void csr_write_mtvec(uint_xlen_t value) {

__asm__ volatile ("csrw mtvec, %0"

: /* output: none */

: "r" (value) /* input : from register */

: /* clobbers: none */);

}

static inline uint_xlen_t csr_read_write_mtvec(uint_xlen_t new_value) {

uint_xlen_t prev_value;

__asm__ volatile ("csrrw %0, mtvec, %1"

: "=r" (prev_value) /* output: register %0 */

: "r" (new_value) /* input : register */

: /* clobbers: none */);

return prev_value;

}

static inline void csr_set_bits_mtvec(uint_xlen_t mask) {

__asm__ volatile ("csrrs zero, mtvec, %0"

: /* output: none */

: "r" (mask) /* input : register */

: /* clobbers: none */);

}

static inline void csr_clr_bits_mtvec(uint_xlen_t mask) {

__asm__ volatile ("csrrc zero, mtvec, %0"

: /* output: none */

: "r" (mask) /* input : register */

: /* clobbers: none */);

}

static inline uint_xlen_t csr_read_set_bits_mtvec(uint_xlen_t mask) {

uint_xlen_t value;

__asm__ volatile ("csrrs %0, mtvec, %1"

: "=r" (value) /* output: register %0 */

: "r" (mask) /* input : register */

: /* clobbers: none */);

return value;

}

static inline uint_xlen_t csr_read_clr_bits_mtvec(uint_xlen_t mask) {

uint_xlen_t value;

__asm__ volatile ("csrrc %0, mtvec, %1"

: "=r" (value) /* output: register %0 */

: "r" (mask) /* input : register */

: /* clobbers: none */);

return value;

}

#define CSR_WRITE_IMM_MTVEC(VALUE) \

__asm__ volatile ("csrrwi zero, mtvec, %0" \

: /* output: none */ \

: "i" (VALUE) /* input : immediate */ \

: /* clobbers: none */)

#define CSR_SET_BITS_IMM_MTVEC(MASK) \

__asm__ volatile ("csrrsi zero, mtvec, %0" \

: /* output: none */ \

: "i" (MASK) /* input : immediate */ \

: /* clobbers: none */)

#define CSR_CLR_BITS_IMM_MTVEC(MASK) \

__asm__ volatile ("csrrci zero, mtvec, %0" \

: /* output: none */ \

: "i" (MASK) /* input : immediate */ \

: /* clobbers: none */)

#define MTVEC_BASE_BIT_OFFSET 2

#define MTVEC_BASE_BIT_WIDTH ((__riscv_xlen-1)-(2) + 1)

#define MTVEC_BASE_BIT_MASK ((1UL<<(((__riscv_xlen-1)-(2) + 1)-1)) << (2))

#define MTVEC_BASE_ALL_SET_MASK ((1UL<<(((__riscv_xlen-1)-(2) + 1)-1)) << (0))

#define MTVEC_MODE_BIT_OFFSET 0

#define MTVEC_MODE_BIT_WIDTH 2

#define MTVEC_MODE_BIT_MASK 0x3

#define MTVEC_MODE_ALL_SET_MASK 0x3

static inline uint_xlen_t csr_read_medeleg(void) {

uint_xlen_t value;

__asm__ volatile ("csrr %0, medeleg"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline void csr_write_medeleg(uint_xlen_t value) {

__asm__ volatile ("csrw medeleg, %0"

: /* output: none */

: "r" (value) /* input : from register */

: /* clobbers: none */);

}

static inline uint_xlen_t csr_read_write_medeleg(uint_xlen_t new_value) {

uint_xlen_t prev_value;

__asm__ volatile ("csrrw %0, medeleg, %1"

: "=r" (prev_value) /* output: register %0 */

: "r" (new_value) /* input : register */

: /* clobbers: none */);

return prev_value;

}

static inline uint_xlen_t csr_read_mideleg(void) {

uint_xlen_t value;

__asm__ volatile ("csrr %0, mideleg"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline void csr_write_mideleg(uint_xlen_t value) {

__asm__ volatile ("csrw mideleg, %0"

: /* output: none */

: "r" (value) /* input : from register */

: /* clobbers: none */);

}

static inline uint_xlen_t csr_read_write_mideleg(uint_xlen_t new_value) {

uint_xlen_t prev_value;

__asm__ volatile ("csrrw %0, mideleg, %1"

: "=r" (prev_value) /* output: register %0 */

: "r" (new_value) /* input : register */

: /* clobbers: none */);

return prev_value;

}

static inline uint_xlen_t csr_read_mip(void) {

uint_xlen_t value;

__asm__ volatile ("csrr %0, mip"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline void csr_write_mip(uint_xlen_t value) {

__asm__ volatile ("csrw mip, %0"

: /* output: none */

: "r" (value) /* input : from register */

: /* clobbers: none */);

}

static inline uint_xlen_t csr_read_write_mip(uint_xlen_t new_value) {

uint_xlen_t prev_value;

__asm__ volatile ("csrrw %0, mip, %1"

: "=r" (prev_value) /* output: register %0 */

: "r" (new_value) /* input : register */

: /* clobbers: none */);

return prev_value;

}

static inline void csr_set_bits_mip(uint_xlen_t mask) {

__asm__ volatile ("csrrs zero, mip, %0"

: /* output: none */

: "r" (mask) /* input : register */

: /* clobbers: none */);

}

static inline void csr_clr_bits_mip(uint_xlen_t mask) {

__asm__ volatile ("csrrc zero, mip, %0"

: /* output: none */

: "r" (mask) /* input : register */

: /* clobbers: none */);

}

static inline uint_xlen_t csr_read_set_bits_mip(uint_xlen_t mask) {

uint_xlen_t value;

__asm__ volatile ("csrrs %0, mip, %1"

: "=r" (value) /* output: register %0 */

: "r" (mask) /* input : register */

: /* clobbers: none */);

return value;

}

static inline uint_xlen_t csr_read_clr_bits_mip(uint_xlen_t mask) {

uint_xlen_t value;

__asm__ volatile ("csrrc %0, mip, %1"

: "=r" (value) /* output: register %0 */

: "r" (mask) /* input : register */

: /* clobbers: none */);

return value;

}

#define CSR_WRITE_IMM_MIP(VALUE) \

__asm__ volatile ("csrrwi zero, mip, %0" \

: /* output: none */ \

: "i" (VALUE) /* input : immediate */ \

: /* clobbers: none */)

#define CSR_SET_BITS_IMM_MIP(MASK) \

__asm__ volatile ("csrrsi zero, mip, %0" \

: /* output: none */ \

: "i" (MASK) /* input : immediate */ \

: /* clobbers: none */)

#define CSR_CLR_BITS_IMM_MIP(MASK) \

__asm__ volatile ("csrrci zero, mip, %0" \

: /* output: none */ \

: "i" (MASK) /* input : immediate */ \

: /* clobbers: none */)

#define MIP_MSI_BIT_OFFSET 3

#define MIP_MSI_BIT_WIDTH 1

#define MIP_MSI_BIT_MASK 0x8

#define MIP_MSI_ALL_SET_MASK 0x1

#define MIP_MTI_BIT_OFFSET 7

#define MIP_MTI_BIT_WIDTH 1

#define MIP_MTI_BIT_MASK 0x80

#define MIP_MTI_ALL_SET_MASK 0x1

#define MIP_MEI_BIT_OFFSET 11

#define MIP_MEI_BIT_WIDTH 1

#define MIP_MEI_BIT_MASK 0x800

#define MIP_MEI_ALL_SET_MASK 0x1

#define MIP_SSI_BIT_OFFSET 1

#define MIP_SSI_BIT_WIDTH 1

#define MIP_SSI_BIT_MASK 0x2

#define MIP_SSI_ALL_SET_MASK 0x1

#define MIP_STI_BIT_OFFSET 5

#define MIP_STI_BIT_WIDTH 1

#define MIP_STI_BIT_MASK 0x20

#define MIP_STI_ALL_SET_MASK 0x1

#define MIP_SEI_BIT_OFFSET 9

#define MIP_SEI_BIT_WIDTH 1

#define MIP_SEI_BIT_MASK 0x200

#define MIP_SEI_ALL_SET_MASK 0x1

#define MIP_USI_BIT_OFFSET 0

#define MIP_USI_BIT_WIDTH 1

#define MIP_USI_BIT_MASK 0x1

#define MIP_USI_ALL_SET_MASK 0x1

#define MIP_UTI_BIT_OFFSET 4

#define MIP_UTI_BIT_WIDTH 1

#define MIP_UTI_BIT_MASK 0x10

#define MIP_UTI_ALL_SET_MASK 0x1

#define MIP_UEI_BIT_OFFSET 8

#define MIP_UEI_BIT_WIDTH 1

#define MIP_UEI_BIT_MASK 0x100

#define MIP_UEI_ALL_SET_MASK 0x1

#define MIP_PLATFORM_DEFINED_BIT_OFFSET 16

#define MIP_PLATFORM_DEFINED_BIT_WIDTH ((__riscv_xlen)-(16) + 1)

#define MIP_PLATFORM_DEFINED_BIT_MASK ((1UL<<(((__riscv_xlen)-(16) + 1)-1)) << (16))

#define MIP_PLATFORM_DEFINED_ALL_SET_MASK ((1UL<<(((__riscv_xlen)-(16) + 1)-1)) << (0))

static inline uint_xlen_t csr_read_mie(void) {

uint_xlen_t value;

__asm__ volatile ("csrr %0, mie"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline void csr_write_mie(uint_xlen_t value) {

__asm__ volatile ("csrw mie, %0"

: /* output: none */

: "r" (value) /* input : from register */

: /* clobbers: none */);

}

static inline uint_xlen_t csr_read_write_mie(uint_xlen_t new_value) {

uint_xlen_t prev_value;

__asm__ volatile ("csrrw %0, mie, %1"

: "=r" (prev_value) /* output: register %0 */

: "r" (new_value) /* input : register */

: /* clobbers: none */);

return prev_value;

}

static inline void csr_set_bits_mie(uint_xlen_t mask) {

__asm__ volatile ("csrrs zero, mie, %0"

: /* output: none */

: "r" (mask) /* input : register */

: /* clobbers: none */);

}

static inline void csr_clr_bits_mie(uint_xlen_t mask) {

__asm__ volatile ("csrrc zero, mie, %0"

: /* output: none */

: "r" (mask) /* input : register */

: /* clobbers: none */);

}

static inline uint_xlen_t csr_read_set_bits_mie(uint_xlen_t mask) {

uint_xlen_t value;

__asm__ volatile ("csrrs %0, mie, %1"

: "=r" (value) /* output: register %0 */

: "r" (mask) /* input : register */

: /* clobbers: none */);

return value;

}

static inline uint_xlen_t csr_read_clr_bits_mie(uint_xlen_t mask) {

uint_xlen_t value;

__asm__ volatile ("csrrc %0, mie, %1"

: "=r" (value) /* output: register %0 */

: "r" (mask) /* input : register */

: /* clobbers: none */);

return value;

}

#define CSR_WRITE_IMM_MIE(VALUE) \

__asm__ volatile ("csrrwi zero, mie, %0" \

: /* output: none */ \

: "i" (VALUE) /* input : immediate */ \

: /* clobbers: none */)

#define CSR_SET_BITS_IMM_MIE(MASK) \

__asm__ volatile ("csrrsi zero, mie, %0" \

: /* output: none */ \

: "i" (MASK) /* input : immediate */ \

: /* clobbers: none */)

#define CSR_CLR_BITS_IMM_MIE(MASK) \

__asm__ volatile ("csrrci zero, mie, %0" \

: /* output: none */ \

: "i" (MASK) /* input : immediate */ \

: /* clobbers: none */)

#define MIE_MSI_BIT_OFFSET 3

#define MIE_MSI_BIT_WIDTH 1

#define MIE_MSI_BIT_MASK 0x8

#define MIE_MSI_ALL_SET_MASK 0x1

#define MIE_MTI_BIT_OFFSET 7

#define MIE_MTI_BIT_WIDTH 1

#define MIE_MTI_BIT_MASK 0x80

#define MIE_MTI_ALL_SET_MASK 0x1

#define MIE_MEI_BIT_OFFSET 11

#define MIE_MEI_BIT_WIDTH 1

#define MIE_MEI_BIT_MASK 0x800

#define MIE_MEI_ALL_SET_MASK 0x1

#define MIE_SSI_BIT_OFFSET 1

#define MIE_SSI_BIT_WIDTH 1

#define MIE_SSI_BIT_MASK 0x2

#define MIE_SSI_ALL_SET_MASK 0x1

#define MIE_STI_BIT_OFFSET 5

#define MIE_STI_BIT_WIDTH 1

#define MIE_STI_BIT_MASK 0x20

#define MIE_STI_ALL_SET_MASK 0x1

#define MIE_SEI_BIT_OFFSET 9

#define MIE_SEI_BIT_WIDTH 1

#define MIE_SEI_BIT_MASK 0x200

#define MIE_SEI_ALL_SET_MASK 0x1

#define MIE_USI_BIT_OFFSET 0

#define MIE_USI_BIT_WIDTH 1

#define MIE_USI_BIT_MASK 0x1

#define MIE_USI_ALL_SET_MASK 0x1

#define MIE_UTI_BIT_OFFSET 4

#define MIE_UTI_BIT_WIDTH 1

#define MIE_UTI_BIT_MASK 0x10

#define MIE_UTI_ALL_SET_MASK 0x1

#define MIE_UEI_BIT_OFFSET 8

#define MIE_UEI_BIT_WIDTH 1

#define MIE_UEI_BIT_MASK 0x100

#define MIE_UEI_ALL_SET_MASK 0x1

#define MIE_PLATFORM_DEFINED_BIT_OFFSET 16

#define MIE_PLATFORM_DEFINED_BIT_WIDTH ((__riscv_xlen)-(16) + 1)

#define MIE_PLATFORM_DEFINED_BIT_MASK ((1UL<<(((__riscv_xlen)-(16) + 1)-1)) << (16))

#define MIE_PLATFORM_DEFINED_ALL_SET_MASK ((1UL<<(((__riscv_xlen)-(16) + 1)-1)) << (0))

static inline uint32_t csr_read_mcountinhibit(void) {

uint_csr32_t value;

__asm__ volatile ("csrr %0, mcountinhibit"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline void csr_write_mcountinhibit(uint_csr32_t value) {

__asm__ volatile ("csrw mcountinhibit, %0"

: /* output: none */

: "r" (value) /* input : from register */

: /* clobbers: none */);

}

static inline uint32_t csr_read_write_mcountinhibit(uint32_t new_value) {

uint_csr32_t prev_value;

__asm__ volatile ("csrrw %0, mcountinhibit, %1"

: "=r" (prev_value) /* output: register %0 */

: "r" (new_value) /* input : register */

: /* clobbers: none */);

return prev_value;

}

static inline void csr_set_bits_mcountinhibit(uint32_t mask) {

__asm__ volatile ("csrrs zero, mcountinhibit, %0"

: /* output: none */

: "r" (mask) /* input : register */

: /* clobbers: none */);

}

static inline void csr_clr_bits_mcountinhibit(uint32_t mask) {

__asm__ volatile ("csrrc zero, mcountinhibit, %0"

: /* output: none */

: "r" (mask) /* input : register */

: /* clobbers: none */);

}

static inline uint32_t csr_read_set_bits_mcountinhibit(uint32_t mask) {

uint_csr32_t value;

__asm__ volatile ("csrrs %0, mcountinhibit, %1"

: "=r" (value) /* output: register %0 */

: "r" (mask) /* input : register */

: /* clobbers: none */);

return value;

}

static inline uint32_t csr_read_clr_bits_mcountinhibit(uint32_t mask) {

uint_csr32_t value;

__asm__ volatile ("csrrc %0, mcountinhibit, %1"

: "=r" (value) /* output: register %0 */

: "r" (mask) /* input : register */

: /* clobbers: none */);

return value;

}

#define CSR_WRITE_IMM_MCOUNTINHIBIT(VALUE) \

__asm__ volatile ("csrrwi zero, mcountinhibit, %0" \

: /* output: none */ \

: "i" (VALUE) /* input : immediate */ \

: /* clobbers: none */)

#define CSR_SET_BITS_IMM_MCOUNTINHIBIT(MASK) \

__asm__ volatile ("csrrsi zero, mcountinhibit, %0" \

: /* output: none */ \

: "i" (MASK) /* input : immediate */ \

: /* clobbers: none */)

#define CSR_CLR_BITS_IMM_MCOUNTINHIBIT(MASK) \

__asm__ volatile ("csrrci zero, mcountinhibit, %0" \

: /* output: none */ \

: "i" (MASK) /* input : immediate */ \

: /* clobbers: none */)

#define MCOUNTINHIBIT_CY_BIT_OFFSET 0

#define MCOUNTINHIBIT_CY_BIT_WIDTH 1

#define MCOUNTINHIBIT_CY_BIT_MASK 0x1

#define MCOUNTINHIBIT_CY_ALL_SET_MASK 0x1

#define MCOUNTINHIBIT_IR_BIT_OFFSET 2

#define MCOUNTINHIBIT_IR_BIT_WIDTH 1

#define MCOUNTINHIBIT_IR_BIT_MASK 0x4

#define MCOUNTINHIBIT_IR_ALL_SET_MASK 0x1

#define MCOUNTINHIBIT_HPM_BIT_OFFSET 3

#define MCOUNTINHIBIT_HPM_BIT_WIDTH 29

#define MCOUNTINHIBIT_HPM_BIT_MASK 0xfffffff8

#define MCOUNTINHIBIT_HPM_ALL_SET_MASK 0x1fffffff

static inline uint64_t csr_read_mcycle(void) {

uint_csr64_t value;

__asm__ volatile ("csrr %0, mcycle"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline void csr_write_mcycle(uint_csr64_t value) {

__asm__ volatile ("csrw mcycle, %0"

: /* output: none */

: "r" (value) /* input : from register */

: /* clobbers: none */);

}

static inline uint64_t csr_read_write_mcycle(uint64_t new_value) {

uint_csr64_t prev_value;

__asm__ volatile ("csrrw %0, mcycle, %1"

: "=r" (prev_value) /* output: register %0 */

: "r" (new_value) /* input : register */

: /* clobbers: none */);

return prev_value;

}

static inline uint64_t csr_read_minstret(void) {

uint_csr64_t value;

__asm__ volatile ("csrr %0, minstret"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline void csr_write_minstret(uint_csr64_t value) {

__asm__ volatile ("csrw minstret, %0"

: /* output: none */

: "r" (value) /* input : from register */

: /* clobbers: none */);

}

static inline uint64_t csr_read_write_minstret(uint64_t new_value) {

uint_csr64_t prev_value;

__asm__ volatile ("csrrw %0, minstret, %1"

: "=r" (prev_value) /* output: register %0 */

: "r" (new_value) /* input : register */

: /* clobbers: none */);

return prev_value;

}

static inline uint64_t csr_read_mhpmcounter3(void) {

uint_csr64_t value;

__asm__ volatile ("csrr %0, mhpmcounter3"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline void csr_write_mhpmcounter3(uint_csr64_t value) {

__asm__ volatile ("csrw mhpmcounter3, %0"

: /* output: none */

: "r" (value) /* input : from register */

: /* clobbers: none */);

}

static inline uint64_t csr_read_write_mhpmcounter3(uint64_t new_value) {

uint_csr64_t prev_value;

__asm__ volatile ("csrrw %0, mhpmcounter3, %1"

: "=r" (prev_value) /* output: register %0 */

: "r" (new_value) /* input : register */

: /* clobbers: none */);

return prev_value;

}

static inline uint_xlen_t csr_read_mhpmevent3(void) {

uint_xlen_t value;

__asm__ volatile ("csrr %0, mhpmevent3"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline void csr_write_mhpmevent3(uint_xlen_t value) {

__asm__ volatile ("csrw mhpmevent3, %0"

: /* output: none */

: "r" (value) /* input : from register */

: /* clobbers: none */);

}

static inline uint_xlen_t csr_read_write_mhpmevent3(uint_xlen_t new_value) {

uint_xlen_t prev_value;

__asm__ volatile ("csrrw %0, mhpmevent3, %1"

: "=r" (prev_value) /* output: register %0 */

: "r" (new_value) /* input : register */

: /* clobbers: none */);

return prev_value;

}

static inline uint32_t csr_read_mcounteren(void) {

uint_csr32_t value;

__asm__ volatile ("csrr %0, mcounteren"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline void csr_write_mcounteren(uint_csr32_t value) {

__asm__ volatile ("csrw mcounteren, %0"

: /* output: none */

: "r" (value) /* input : from register */

: /* clobbers: none */);

}

static inline uint32_t csr_read_write_mcounteren(uint32_t new_value) {

uint_csr32_t prev_value;

__asm__ volatile ("csrrw %0, mcounteren, %1"

: "=r" (prev_value) /* output: register %0 */

: "r" (new_value) /* input : register */

: /* clobbers: none */);

return prev_value;

}

static inline void csr_set_bits_mcounteren(uint32_t mask) {

__asm__ volatile ("csrrs zero, mcounteren, %0"

: /* output: none */

: "r" (mask) /* input : register */

: /* clobbers: none */);

}

static inline void csr_clr_bits_mcounteren(uint32_t mask) {

__asm__ volatile ("csrrc zero, mcounteren, %0"

: /* output: none */

: "r" (mask) /* input : register */

: /* clobbers: none */);

}

static inline uint32_t csr_read_set_bits_mcounteren(uint32_t mask) {

uint_csr32_t value;

__asm__ volatile ("csrrs %0, mcounteren, %1"

: "=r" (value) /* output: register %0 */

: "r" (mask) /* input : register */

: /* clobbers: none */);

return value;

}

static inline uint32_t csr_read_clr_bits_mcounteren(uint32_t mask) {

uint_csr32_t value;

__asm__ volatile ("csrrc %0, mcounteren, %1"

: "=r" (value) /* output: register %0 */

: "r" (mask) /* input : register */

: /* clobbers: none */);

return value;

}

#define CSR_WRITE_IMM_MCOUNTEREN(VALUE) \

__asm__ volatile ("csrrwi zero, mcounteren, %0" \

: /* output: none */ \

: "i" (VALUE) /* input : immediate */ \

: /* clobbers: none */)

#define CSR_SET_BITS_IMM_MCOUNTEREN(MASK) \

__asm__ volatile ("csrrsi zero, mcounteren, %0" \

: /* output: none */ \

: "i" (MASK) /* input : immediate */ \

: /* clobbers: none */)

#define CSR_CLR_BITS_IMM_MCOUNTEREN(MASK) \

__asm__ volatile ("csrrci zero, mcounteren, %0" \

: /* output: none */ \

: "i" (MASK) /* input : immediate */ \

: /* clobbers: none */)

#define MCOUNTEREN_CY_BIT_OFFSET 0

#define MCOUNTEREN_CY_BIT_WIDTH 1

#define MCOUNTEREN_CY_BIT_MASK 0x1

#define MCOUNTEREN_CY_ALL_SET_MASK 0x1

#define MCOUNTEREN_TM_BIT_OFFSET 1

#define MCOUNTEREN_TM_BIT_WIDTH 1

#define MCOUNTEREN_TM_BIT_MASK 0x2

#define MCOUNTEREN_TM_ALL_SET_MASK 0x1

#define MCOUNTEREN_IR_BIT_OFFSET 2

#define MCOUNTEREN_IR_BIT_WIDTH 1

#define MCOUNTEREN_IR_BIT_MASK 0x4

#define MCOUNTEREN_IR_ALL_SET_MASK 0x1

#define MCOUNTEREN_HPM_BIT_OFFSET 3

#define MCOUNTEREN_HPM_BIT_WIDTH 29

#define MCOUNTEREN_HPM_BIT_MASK 0xfffffff8

#define MCOUNTEREN_HPM_ALL_SET_MASK 0x1fffffff

static inline uint_xlen_t csr_read_scounteren(void) {

uint_xlen_t value;

__asm__ volatile ("csrr %0, scounteren"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline void csr_write_scounteren(uint_xlen_t value) {

__asm__ volatile ("csrw scounteren, %0"

: /* output: none */

: "r" (value) /* input : from register */

: /* clobbers: none */);

}

static inline uint_xlen_t csr_read_write_scounteren(uint_xlen_t new_value) {

uint_xlen_t prev_value;

__asm__ volatile ("csrrw %0, scounteren, %1"

: "=r" (prev_value) /* output: register %0 */

: "r" (new_value) /* input : register */

: /* clobbers: none */);

return prev_value;

}

static inline uint_xlen_t csr_read_mscratch(void) {

uint_xlen_t value;

__asm__ volatile ("csrr %0, mscratch"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline void csr_write_mscratch(uint_xlen_t value) {

__asm__ volatile ("csrw mscratch, %0"

: /* output: none */

: "r" (value) /* input : from register */

: /* clobbers: none */);

}

static inline uint_xlen_t csr_read_write_mscratch(uint_xlen_t new_value) {

uint_xlen_t prev_value;

__asm__ volatile ("csrrw %0, mscratch, %1"

: "=r" (prev_value) /* output: register %0 */

: "r" (new_value) /* input : register */

: /* clobbers: none */);

return prev_value;

}

static inline uint_xlen_t csr_read_mepc(void) {

uint_xlen_t value;

__asm__ volatile ("csrr %0, mepc"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline void csr_write_mepc(uint_xlen_t value) {

__asm__ volatile ("csrw mepc, %0"

: /* output: none */

: "r" (value) /* input : from register */

: /* clobbers: none */);

}

static inline uint_xlen_t csr_read_write_mepc(uint_xlen_t new_value) {

uint_xlen_t prev_value;

__asm__ volatile ("csrrw %0, mepc, %1"

: "=r" (prev_value) /* output: register %0 */

: "r" (new_value) /* input : register */

: /* clobbers: none */);

return prev_value;

}

static inline uint_xlen_t csr_read_mcause(void) {

uint_xlen_t value;

__asm__ volatile ("csrr %0, mcause"

: "=r" (value) /* output : register */

: /* input : none */

: /* clobbers: none */);

return value;

}

static inline void csr_write_mcause(uint_xlen_t value) {

__asm__ volatile ("csrw mcause, %0"

: /* output: none */

: "r" (value) /* input : from register */

: /* clobbers: none */);

}

static inline uint_xlen_t csr_read_write_mcause(uint_xlen_t new_value) {

uint_xlen_t prev_value;

__asm__ volatile ("csrrw %0, mcause, %1"

: "=r" (prev_value) /* output: register %0 */

: "r" (new_value) /* input : register */

: /* clobbers: none */);

return prev_value;

}

static inline void csr_set_bits_mcause(uint_xlen_t mask) {

__asm__ volatile ("csrrs zero, mcause, %0"

: /* output: none */

: "r" (mask) /* input : register */

: /* clobbers: none */);

}

static inline void csr_clr_bits_mcause(uint_xlen_t mask) {

__asm__ volatile ("csrrc zero, mcause, %0"

: /* output: none */

: "r" (mask) /* input : register */

: /* clobbers: none */);

}

static inline uint_xlen_t csr_read_set_bits_mcause(uint_xlen_t mask) {

uint_xlen_t value;