Using latest 6502bench sourcegen 1.10.0
I have big endian address list like this on the project:
AddrTable0 .DBD2 TA8D0
.DBD2 T516C
.DBD2 TA8DC
.DBD2 T516C
.DBD2 TA8E8
.DBD2 T5178
.DBD2 TA8F4
.DBD2 T5178
.DBD2 TA900
.DBD2 T5178
.DBD2 TA90C
.DBD2 T516C
.DBD2 TA918
.DBD2 T519C
.DBD2 TA924
.DBD2 T5190
and it generates to:
AddrTable0 .byte $A8,$D0
.byte $51,$6C
.byte $A8,$DC
.byte $51,$6C
.byte $A8,$E8
.byte $51,$78
.byte $A8,$F4
.byte $51,$78
.byte $A9,$00
.byte $51,$78
.byte $A9,$0C
.byte $51,$6C
.byte $A9,$18
.byte $51,$9C
.byte $A9,$24
.byte $51,$90
I'd assume it should generate something like:
.byte >TA8D0
.byte <TA8D0
Using latest 6502bench sourcegen 1.10.0
I have big endian address list like this on the project:
AddrTable0 .DBD2 TA8D0
.DBD2 T516C
.DBD2 TA8DC
.DBD2 T516C
.DBD2 TA8E8
.DBD2 T5178
.DBD2 TA8F4
.DBD2 T5178
.DBD2 TA900
.DBD2 T5178
.DBD2 TA90C
.DBD2 T516C
.DBD2 TA918
.DBD2 T519C
.DBD2 TA924
.DBD2 T5190
and it generates to:
AddrTable0 .byte $A8,$D0
.byte $51,$6C
.byte $A8,$DC
.byte $51,$6C
.byte $A8,$E8
.byte $51,$78
.byte $A8,$F4
.byte $51,$78
.byte $A9,$00
.byte $51,$78
.byte $A9,$0C
.byte $51,$6C
.byte $A9,$18
.byte $51,$9C
.byte $A9,$24
.byte $51,$90
I'd assume it should generate something like:
.byte >TA8D0
.byte <TA8D0