The BUFGMUX instance in gmii.py creates generates the following error when build for the Panologic-g2 platform base on a Spartan 6 xc6slx150. The error message is:
ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found
that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
IOB component <eth_clocks_rx> is placed at site . The corresponding
BUFG component <eth_rx_clk_BUFG> is placed at site <BUFGMUX_X3Y5>. There is
only a select set of IOBs that can use the fast path to the Clocker buffer,
and they are not being used. You may want to analyze why this problem exists
and correct it. If this sub optimal condition is acceptable for this design,
you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote
this message to a WARNING and allow your design to continue. However, the use
of this override is highly discouraged as it may lead to very poor timing
results. It is recommended that this error condition be corrected in the
design. A list of all the COMP.PINs used in this clock placement rule is
listed below. These examples can be used directly in the .ucf file to
override this clock rule.
< NET "eth_clocks_rx" CLOCK_DEDICATED_ROUTE = FALSE; >
After a LOT of study of Table 1-2: Shared Global Clocking Resources for Bank 2 and Bank 3" in ug382.pdf I've concluded (rightly for wrongly) that with eth_clocks_rx on GCLK_28 and eth_clocks_tx on GCLK_29 this is indeed unroutable.
I was able to get liteeth to work by replacing the BUFGMUX with simple combinational logic, but I'm not confident of my fix even thou "it seems to work".
My changes can be found here: https://github.com/skiphansen/liteeth/tree/pano_fixes.
The BUFGMUX instance in gmii.py creates generates the following error when build for the Panologic-g2 platform base on a Spartan 6 xc6slx150. The error message is:
ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found
that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
IOB component <eth_clocks_rx> is placed at site . The corresponding
BUFG component <eth_rx_clk_BUFG> is placed at site <BUFGMUX_X3Y5>. There is
only a select set of IOBs that can use the fast path to the Clocker buffer,
and they are not being used. You may want to analyze why this problem exists
and correct it. If this sub optimal condition is acceptable for this design,
you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote
this message to a WARNING and allow your design to continue. However, the use
of this override is highly discouraged as it may lead to very poor timing
results. It is recommended that this error condition be corrected in the
design. A list of all the COMP.PINs used in this clock placement rule is
listed below. These examples can be used directly in the .ucf file to
override this clock rule.
< NET "eth_clocks_rx" CLOCK_DEDICATED_ROUTE = FALSE; >
After a LOT of study of Table 1-2: Shared Global Clocking Resources for Bank 2 and Bank 3" in ug382.pdf I've concluded (rightly for wrongly) that with eth_clocks_rx on GCLK_28 and eth_clocks_tx on GCLK_29 this is indeed unroutable.
I was able to get liteeth to work by replacing the BUFGMUX with simple combinational logic, but I'm not confident of my fix even thou "it seems to work".
My changes can be found here: https://github.com/skiphansen/liteeth/tree/pano_fixes.